Power Switch Circuit Layout for Higher-Density Semiconductor Chips
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Solution Overview
Problem
Conventional semiconductor devices face a reduction in power supply capacity due to the need for larger power switch circuits, which increases the size of the vacant area and subsequently reduces the size of logic circuits, leading to increased chip size and decreased integration density.
Innovation Solution
The implementation of additional transistors in the vacant areas of power switch circuits, matching the size and structure of transistors in logic circuits, enhances power supply capacity without increasing the layout area by alleviating shape variation and electrical characteristics, thereby maintaining logic circuit size and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger transistors are used in power switch circuits to reduce leakage current, then leakage current is reduced, but the chip size increases and logic circuit area decreases
Solution Approach 1:
The power switch circuit is divided into multiple segments: a first power switch circuit with a first transistor larger than logic circuit transistors, and a second power switch circuit with second transistors of the same size as logic circuit transistors. This segmentation allows different transistor sizes to serve different functions while sharing the same layout area, thereby reducing leakage current without sacrificing logic circuit area.
2Power
If larger transistors are used in power switch circuits to increase power supply capacity, then power supply capacity is improved, but the chip size increases
Solution Approach 1:
The first power switch circuit and second power switch circuit are merged into a single integrated structure that shares common power lines and control logic. The first transistor (larger size) and second transistors (same size as logic circuit transistors) are combined in parallel to provide enhanced power supply capacity without proportionally increasing chip area, as they share the same layout space through efficient area utilization.
3Manufacturing precision
If vacant areas are provided in power switch circuits to minimize shape variations, then manufacturing precision is improved, but the chip size increases
Solution Approach 1:
The vacant area in the power switch circuit layout is utilized for multiple purposes: it serves as a buffer to minimize shape variations and improve manufacturing precision, while simultaneously being shared by both the first and second power switch circuits. This multi-functional use of the vacant area allows manufacturing precision to be improved without proportionally increasing chip size.
Data Source
AI summary
A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.