Semiconductor Power Switch Layout for Low-IR-Drop Power Domains
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Solution Overview
Problem
Existing semiconductor devices lack a detailed configuration for providing a power switch circuit in secondary semiconductor chips with interconnections, which affects power management and efficiency.
Innovation Solution
A semiconductor device configuration that includes a first chip with a substrate and interconnection layers, and a second chip with a power switch circuit positioned between power domains, utilizing switch transistors and control signal lines to manage power potential and ground connections efficiently, reducing size and IR drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a power switch circuit is provided in a secondary semiconductor chip with interconnections, then power management capability is improved, but device complexity increases
Solution Approach 1:
The semiconductor device is divided into a first chip containing logic circuits and a second chip containing the power switch circuit. This segmentation allows the power management function to be added without complicating the main logic chip, as the switch circuit resides in a separate secondary chip with its own interconnections.
Solution Approach 2:
The secondary semiconductor chip acts as an intermediary between the power supply and the logic circuits. It includes interconnections that deliver power potential to the logic circuits while containing the power switch circuit, thus mediating power management without requiring direct integration in the main chip.
2Power
If power lines are extended to supply power potential, then power distribution capability is improved, but IR drops increase
Solution Approach 1:
The second chip serves as an intermediary power distribution node that contains the switch circuit. By placing the switch in the secondary chip rather than extending power lines throughout the entire device, the patent reduces the length of power lines and minimizes IR drops while maintaining power distribution capability.
3Volume of moving object
If the semiconductor device size is reduced, then integration density is improved, but heat dissipation becomes more difficult
Solution Approach 1:
Dividing the device into two separate chips allows for optimized thermal management. The second chip containing the power switch circuit can be positioned and connected in a way that facilitates heat dissipation, while the first chip maintains compact logic circuit integration, thus reducing overall device size without compromising heat dissipation.
Data Source
AI summary
A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.