Power Switch Circuit Layout for Narrow Macro Gaps and IR-Drop
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Solution Overview
Problem
The existing power gating technique for semiconductor integrated circuit devices faces challenges in arranging power switch circuits to avoid overlapping with macros, leading to increased power supply voltage fluctuations (IR-Drop) and reduced usable standard cell area and wiring resources, resulting in potential rework during the design process.
Innovation Solution
A method is introduced to detect narrow areas within the circuit arrangement where power switch circuits are arranged differently from the standard staircase pattern, using a second rule to minimize IR-Drop and optimize wiring resources, while maintaining the staircase pattern in other areas to ensure efficient power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If power switch circuits are arranged in a regular staircase pattern, then arrangement regularity is improved, but power supply voltage fluctuation (IR-Drop) increases when macros overlap with the pattern
Solution Approach 1:
The patent applies local quality by detecting narrow areas where the width is less than a predetermined value and arranging power switch circuits differently in these specific locations compared to regular areas. In narrow areas, power switch circuits are arranged to avoid overlapping with macros, while in other areas, the regular staircase pattern is maintained. This localized adaptation resolves the contradiction by maintaining arrangement regularity in most areas while preventing IR-Drop in critical narrow areas.
2Reliability
If power switch circuits are displaced to avoid overlapping with macros, then power supply voltage fluctuation is reduced, but usable standard cell area and wiring resources are reduced
Solution Approach 1:
The invention applies local quality by selectively displacing power switch circuits only in detected narrow areas where width is less than a predetermined value, rather than uniformly displacing them across the entire circuit arrangement area. This localized approach minimizes the impact on usable standard cell area and wiring resources while still preventing IR-Drop in the specific narrow areas where macro overlap would occur.
3Reliability
If power switch circuits are arranged in narrow areas with different rules, then IR-Drop is reduced, but design complexity increases due to multiple arrangement rules
Solution Approach 1:
The patent applies preliminary action by detecting narrow areas and determining their locations before arranging power switch circuits. This preliminary detection and classification enables the arrangement process to apply appropriate rules for each area without requiring complex real-time decision-making during circuit placement, thereby reducing design complexity while still achieving the goal of minimizing IR-Drop.
Data Source
AI summary
A designing method of a semiconductor integrated circuit device includes: arranging a plurality of macros within a circuit arrangement area of a semiconductor integrated circuit device in which a plurality of power switch circuits are to be arranged in accordance with a first rule; detecting a narrow area from a first area, a width of the narrow area being less than a first value, the first area being an area in which the macros are not arranged within the circuit arrangement area; arranging the power switch circuits in the detected narrow area in accordance with a second rule different from the first rule; and arranging the power switch circuits in an area other than the narrow area within the first area in accordance with the first rule.