Power Switch POR Circuit Using Peaking Current RC Delay

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Solution Overview

Problem

Traditional power-on reset circuits in power switches are limited by fast rise times in Vcc voltage, requiring large resistors and capacitors, leading to area inefficiencies and indeterminate states at voltages below the operating voltage, and lack the ability to provide controlled power-up for successive integrated circuits during transitions.

Innovation Solution

A power-on-reset circuit using a peaking current technique to generate a controlled RC delay, enabling precise stabilization and activation at a predefined voltage, with an active low reset signal for coordinated power management and externally controlled voltage provision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional RC-based POR circuits are used with fast Vcc rise times, then large resistors and capacitors are required, but this leads to significant area consumption on the integrated circuit

Engineering Contradiction:
ImprovePOR functionalityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the fundamental parameters of the POR circuit by replacing the traditional RC time constant approach with a current-controlled delay mechanism. The delay time is determined by the integral of the difference between Vcc and a reference voltage, rather than by fixed R and C values. This allows the circuit to adapt to different Vcc rise times without requiring large passive components, thereby reducing area consumption while maintaining reliable POR functionality.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If traditional POR circuits operate at voltages below the Schmitt trigger operating voltage, then the POR output becomes indeterminate, but raising the operating voltage increases power consumption

Engineering Contradiction:
ImprovePOR output stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent introduces an intermediary mechanism - a current mirror circuit and integrator - that mediates between the Vcc voltage and the POR output. The current mirror copies the difference current between Vcc and Vref, and the integrator accumulates this current to generate a stable delay signal. This intermediary approach allows the circuit to operate reliably at lower voltages without requiring the Schmitt trigger to operate directly at those voltages, thus maintaining output stability while reducing power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If traditional POR circuits are used, then they can only provide a reset impulse at a particular time, but they lack the ability to provide controlled power-up for other components during transition periods

Engineering Contradiction:
Improvepower management capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal POR circuit that can serve multiple functions. The same current mirror and integrator mechanism that generates the reset impulse also provides a controllable delay signal that can be used to sequentially power-up other components in the circuit. The POR circuit becomes multi-functional: it provides both the traditional reset function and a controlled power-up function for successive integrated circuits, thereby increasing adaptability without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables stable and efficient power-up of successive integrated circuits without over-current or over-voltage, ensuring synchronized resets and preventing instability during transitions, while allowing controlled power management for other components.

Implementation Method 1

A controlled peaking current is used in the POR circuit to provide precise RC delay to avoid instability during transition

Methodology Applied
Scientific EffectRC delay: Capacitance

Data Source

PatentUS8004321B2Method of implementing power-on-reset in power switches
Publication Date: 2011.08.23 MICREL INC
  • US8004321B2 patent drawing
  • US8004321B2 patent drawing
  • US8004321B2 patent drawing

AI summary

A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.