Insulated-Gate Power Switch Epitaxy for Precise Dopant Profiles
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Solution Overview
Problem
Conventional fabrication techniques for high power insulated-gate-controlled devices result in imprecise and variable dopant profiles due to high temperature steps, leading to crystalline defects and reduced performance.
Innovation Solution
A low temperature epitaxy (LTE) process is used to grow the n-buffer and p+ layers without additional implantation or high temperature annealing, maintaining precise dopant profiles and reducing crystalline damage, thereby improving the precision and efficiency of the device's regions and boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature annealing is used to activate dopants and reduce crystalline damage, then dopant activation and crystal repair are improved, but dopant diffusion becomes imprecise and variable leading to reduced manufacturing precision
Solution Approach 1:
The patent changes the temperature parameter from high temperature annealing to low temperature epitaxy (below 600°C), which fundamentally alters the physical chemistry of the process. This lower temperature prevents excessive dopant diffusion while still enabling effective dopant incorporation and activation during the epitaxial growth process itself.
Solution Approach 2:
The patent replaces the thermal field-based annealing process with a chemical vapor deposition-based epitaxial growth process. Instead of using high temperature to activate dopants and repair crystals, the invention uses controlled chemical deposition at low temperatures to simultaneously achieve dopant incorporation, activation, and crystal growth, eliminating the need for separate high temperature steps.
2Reliability
If high temperature steps are used in fabrication, then dopant activation is improved, but dopant diffusion becomes variable and imprecise
Solution Approach 1:
The patent performs dopant incorporation and activation during the epitaxial growth process itself, rather than requiring separate subsequent annealing steps. By preparing and activating the dopants in advance during the growth process under controlled conditions, the invention achieves precise dopant profiles without the variability introduced by high temperature diffusion steps.
3Ease of manufacture
If conventional fabrication techniques are used, then manufacturing simplicity is maintained, but crystalline defects increase and performance decreases
Solution Approach 1:
The patent replaces conventional high temperature thermal processing with low temperature epitaxial growth. This substitution maintains fabrication feasibility while dramatically reducing crystalline defects by avoiding the thermal stress and diffusion-related damage that occur during high temperature annealing, thereby improving device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LTE process enhances the performance and repeatability of the device by maintaining precise dopant profiles and reducing crystalline defects, resulting in improved operating characteristics and efficiency.
Implementation Method 1
Employ low temperature epitaxy (LTE) processes to grow n-buffer and p+ layers on the substrate
Data Source
AI summary
A method of forming a layered, high power vertical insulated-gate switch uses an n-type substrate. A p-well is formed by implantation in the top surface of the substrate followed by implanting n-type dopants in the p-well to form n+ source regions. Trenched gates are formed extending through the n+ source regions and into the p-well. The wafer is transferred to a carrier and the bottom surface of the wafer substrate is thinned by CMP. An n-buffer layer is then epitaxially grown on the bottom surface using low temperature epitaxy (LTE). The low temperature does not substantially diffuse the dopants in the overlying regions. A bottom p+ layer is then formed by LTE. Anode and cathode metal electrodes are then formed. The n-buffer layer and p+ layers can be precisely formed for optimal efficiency and the LTE maintains the dopant profiles of the overlying regions.