Power Switch Ramp Rate Control for Low-Noise Power Gating
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Solution Overview
Problem
Integrated circuits face challenges in power management due to leakage currents, which lead to static power consumption and noise on power supply connections, especially in high-performance devices, making it difficult to balance delay and noise during power gating.
Innovation Solution
A power manager circuit is introduced to control the rate at which power switches are enabled in power gated blocks based on parameters like power supply voltage, operating temperature, and process corner parameters, allowing for parallel or serial enabling of power switches and adjusting drive strength to minimize noise and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If power switches are enabled in a serial chain to reduce power supply noise, then power supply noise is reduced, but the delay to enable the power gated block increases
Solution Approach 1:
The patent applies dynamics by making the power switch enablement configuration adjustable based on operating conditions. The system can dynamically switch between serial chain configuration (for low noise requirements) and parallel or partially-parallel configuration (for low delay requirements), allowing optimal performance across varying operating conditions such as different power supply voltages, temperatures, and process corners.
Solution Approach 2:
The patent changes the connectivity parameter of power switches from a fixed serial chain to a configurable arrangement. By adjusting the enablement configuration (serial, parallel, or partially-parallel) based on process voltage temperature (PVT) conditions, the system optimizes the trade-off between noise reduction and enablement delay for different operating scenarios.
2Loss of time
If the rate of change of current is increased to reduce enable delay, then enable delay is reduced, but power supply noise increases
Solution Approach 1:
The system dynamically adjusts the current ramp rate by changing the enablement configuration of power switches. When fast enablement is needed, the system uses parallel or partially-parallel configurations that increase the rate of change of current. When noise reduction is prioritized, the system switches to serial chain configuration that limits the current ramp rate, thus managing the trade-off between enable delay and power supply noise.
Solution Approach 2:
The patent changes the operational parameter of current ramp rate by adjusting how power switches are enabled. Different enablement configurations produce different rates of change in current flow, allowing the system to select appropriate ramp rates based on PVT conditions and performance requirements.
3Loss of time
If more parallel enablement of power switches is used to reduce delay, then enable delay is reduced, but power supply noise increases
Solution Approach 1:
The patent implements dynamic adjustment of power switch enablement parallelism. The system can switch between highly parallel enablement (reducing delay) and more serial enablement (reducing noise) based on real-time operating conditions, making the degree of parallelism a dynamic parameter rather than a fixed design choice.
Solution Approach 2:
The connectivity and enablement timing parameters of power switches are made changeable based on operating conditions. The system adjusts the degree of parallelism in power switch enablement according to PVT conditions, allowing optimization of the delay-noise trade-off for different scenarios.
4Object-affected harmful factors
If serial chain configuration is used to reduce noise, then power supply noise is reduced, but enable delay increases
Solution Approach 1:
The system dynamically selects between serial chain configuration and parallel/partially-parallel configurations based on operating conditions. When noise reduction is the priority, serial chain is used; when fast enablement is needed, parallel configurations are selected, making the configuration adaptive rather than static.
Solution Approach 2:
The patent changes the structural parameter of power switch connectivity from a fixed serial chain to a configurable arrangement. By adjusting the connectivity and enablement timing based on PVT conditions, the system optimizes the trade-off between noise reduction and enablement speed.
Data Source
AI summary
In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.