Power Switch Transistor Sizing for MTCMOS Speed and Voltage Drop
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Solution Overview
Problem
Existing Multi-Threshold CMOS (MTCMOS) logic circuits face speed degradation due to overloaded conditions, primarily caused by large voltage drops at source-drain terminals, which affect the gate-source voltage, leading to reduced speed performance.
Innovation Solution
A method and system for setting the size of power switch transistors by extracting load currents, calculating limited voltage drops, and determining size parameters to maintain high-speed transmission in logic circuits, involving a processing unit that performs load current extraction, voltage drop calculation, standard supply current calculation, simulated supply current calculation, and size setting steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If MTCMOS logic gates are configured with minimum size to reduce power consumption, then power consumption is reduced, but the logic circuit speed becomes overloaded and slows down
Solution Approach 1:
The patent changes the size parameter of power switch transistors based on the specific load current requirements of different logic circuits. By calculating the actual current load and determining appropriate transistor sizes, the system optimizes the balance between power consumption and speed performance, avoiding both oversized transistors that waste power and undersized transistors that cannot maintain speed.
2Speed
If power switch transistor size is increased to maintain high-speed transmission, then speed performance is improved, but area loss increases and standby power consumption increases
Solution Approach 1:
The patent applies local quality by configuring different power switch transistor sizes in different locations based on the specific current load requirements of each logic circuit. Instead of using a uniform minimum size throughout, the system locally adapts transistor dimensions to match actual operational needs, ensuring high-speed performance where required while minimizing area and power elsewhere.
3Reliability
If power switch transistor size is increased to reduce voltage drop, then voltage stability is improved, but standby power consumption increases
Solution Approach 1:
The patent dynamically determines optimal transistor size parameters based on calculated load currents and voltage drop requirements. By changing the size parameter to match actual operational demands rather than using fixed minimum sizes, the system achieves sufficient voltage stability only where and when needed, thereby reducing standby power consumption in circuits with lower current requirements.
Data Source
AI summary
A size setting method for a power switch transistor and a system thereof are proposed. A load current extracting step is performed to extract a first load current and a second load current. A limited voltage drop calculating step is performed to calculate a limited voltage drop according to a speed proportional value, the first load current and the second load current. A standard supply current calculating step is performed to calculate a standard supply current according to the limited voltage drop. A simulated supply current calculating step is performed to calculate a simulated supply current according to the standard supply current, the limited voltage drop and a line voltage value. A size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and set a size of the power switch transistor according to the size parameter.