Power Switch Control Circuit for Low-Leakage Standby Isolation
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in efficiently interrupting power supply to connection destinations while minimizing power consumption and leakage currents during standby states.
Innovation Solution
The semiconductor integrated circuit employs a power switch configuration with control circuits having specific drive strength characteristics and optional assist circuits to manage power supply and interruption, utilizing low threshold voltage transistors to enhance control signal strength and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power switch is used to interrupt power supply, then power supply interruption capability is improved, but leakage current increases during standby states
Solution Approach 1:
The power switch is divided into multiple stages: a first switch element (PMOS) for main power interruption and a second switch element (NMOS) for leakage suppression. This segmentation allows each element to optimize for its specific function, achieving both reliable power interruption and low leakage current during standby states.
Solution Approach 2:
A control circuit acts as an intermediary between the power switch control signal and the switch elements. It generates complementary control signals that coordinate the operation of the PMOS and NMOS elements, ensuring the PMOS turns off for power interruption while the NMOS remains on to suppress leakage current.
2Speed
If control circuits with high drive strength are used, then switching speed is improved, but power consumption increases
Solution Approach 1:
The control circuit uses different drive strength configurations for different switching operations. The first inverter uses a PMOS transistor with larger width-to-length ratio for fast turn-off, while the second inverter uses an NMOS transistor with larger width-to-length ratio for fast turn-on. This local optimization achieves high switching speed without excessive power consumption across all operations.
Solution Approach 2:
The patent adjusts the width-to-length ratios of transistor channels as a parameter to optimize drive strength. By making the PMOS channel wider or the NMOS channel wider in specific inverters, the control circuit achieves asymmetric drive strengths that speed up switching while minimizing the power consumption penalty.
Data Source
AI summary
According to one embodiment, in a semiconductor integrated circuit, a switch is connected between a first power supply and a second power supply. The switch turns off when receiving a first level at a control terminal. A first control circuit includes an input node and an output node. The output node is connected to the control terminal of the switch. A second control circuit includes an output node and an input node. The input node is connected to the control terminal of the switch. The semiconductor integrated circuit satisfies at least one of a condition that drive strength to the first level is greater than drive strength to the second level in the first control circuit and another condition that the drive strength to the second level is greater than the drive strength to the first level in the second control circuit.