Power Switch Cell and TIE Cell ESD Protection in Semiconductor ICs
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in achieving high resistance to electrostatic discharge (ESD) and fast response speeds, particularly in power management and logic circuit operations within shutdown regions.
Innovation Solution
The integration of power switch cells and TIE cells, which include TIE-high and TIE-low cells, are used to manage power supply and output signals within the shutdown region, ensuring high ESD resistance and fast response times by using multi-threshold CMOS technology and strategically placing power switch cells between energization and shutdown regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power switch cells are disposed at the boundary between energization region and power shutdown region to control power supply, then power consumption is reduced, but ESD resistance deteriorates
Solution Approach 1:
The power management structure is segmented into multiple independent power switch cells (first PSW, second PSW) distributed at different locations (boundary and inside shutdown region). This segmentation allows each cell to handle specific power control tasks, reducing the power consumption of individual cells while collectively providing robust ESD protection through redundant paths
Solution Approach 2:
TIE cells are placed inside the shutdown region to beforehand cushion against ESD effects. These cells maintain voltage levels during ESD events, providing prior protection to logic circuits before damage can occur. The TIE cells act as a buffer that absorbs ESD energy and prevents it from reaching vulnerable logic circuits
2Reliability
If TIE cells are used to fix voltage levels instantaneously, then ESD resistance is improved, but device complexity increases
Solution Approach 1:
The TIE cells perform multiple functions: they fix voltage levels during normal operation, provide ESD protection, and maintain logic levels during power transitions. By making these cells multi-functional, the patent reduces the need for separate protection circuits, thereby managing complexity while enhancing ESD resistance
Solution Approach 2:
The patent uses multi-threshold CMOS technology where TIE cells utilize transistors with different threshold voltages (high-threshold and low-threshold MOSFETs). By changing the threshold voltage parameter of transistors in different regions, the circuit achieves fast response for ESD protection while maintaining low leakage current, balancing performance with complexity
3Loss of energy
If high threshold MOSFETs are used in power switch cells, then power leakage is reduced, but response speed deteriorates
Solution Approach 1:
Different threshold voltage characteristics are assigned to different parts of the power switch cell structure. High-threshold MOSFETs are used in specific regions where low leakage is critical, while low-threshold MOSFETs are used in regions where fast response is prioritized. This local differentiation allows simultaneous optimization of both leakage and response speed
Solution Approach 2:
The power switch cell employs a composite transistor structure combining both high-threshold and low-threshold MOSFETs working together. The high-threshold transistors provide low leakage paths while low-threshold transistors provide fast switching paths. This composite approach allows the circuit to achieve both low power leakage and fast response speed by utilizing the complementary strengths of different transistor types
Data Source
AI summary
A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.