Power Switch Wakeup Sequencing for Inrush and Noise Control
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Solution Overview
Problem
Power gating in integrated circuits leads to noise on power supply connections due to changes in current flow, affecting operation and increasing delay in enabling power gated blocks, especially with variations in semiconductor fabrication, voltage, and temperature.
Innovation Solution
A power switch acceleration scheme that uses a virtual voltage node and delay chains to sequentially activate power switches, reducing the delay as voltage increases, thereby accelerating the wakeup process while controlling current inrush and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power switches are activated simultaneously during wakeup, then power-on time is reduced, but current inrush and power supply noise increase
Solution Approach 1:
The power switch activation process is segmented into multiple sequential stages rather than simultaneous activation. The delay chain divides the wakeup process into discrete time intervals, with each stage activating a portion of the power switches. This segmentation reduces the peak current inrush and power supply noise while maintaining relatively fast wakeup time.
2Object-affected harmful factors
If power switches are activated sequentially to reduce current inrush, then power supply noise decreases, but wakeup time increases
Solution Approach 1:
The power switch activation follows a periodic pattern controlled by the delay chain, which introduces regular time intervals between activation stages. This periodic action allows the system to manage current inrush and power supply noise in a controlled manner while maintaining predictable and optimized wakeup timing.
3Object-affected harmful factors
If delay chain is used to control power switch activation timing, then current inrush is reduced, but device complexity increases
Solution Approach 1:
The delay chain acts as an intermediary component between the wakeup signal and the power switches. It mediates the activation process by introducing controlled time delays, thereby reducing current inrush without requiring complex control logic or multiple independent control circuits for each power switch.
4Productivity
If voltage on virtual voltage node increases, then power switch activation rate can be increased, but noise specifications may be exceeded
Solution Approach 1:
The system monitors the voltage level on the virtual voltage node and uses this information to dynamically adjust the power switch activation rate. When voltage reaches certain thresholds, the delay chain parameters are adjusted to increase activation rate, while ensuring that noise specifications are not exceeded through controlled pacing of the activation sequence.
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
A method and apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit (10) includes at least one power gated circuit block (14A-14C). The power gated circuit block (14A-14C) includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block (14A-14C) is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases,. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block (14A-14C). The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.