Power-Switchable Core Yield via Domain Segmentation
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Solution Overview
Problem
Modern integrated circuits with multiple cores face challenges in maintaining high yield due to defects in individual cores, leading to unnecessary discarding of entire chips, as existing test methods fail to isolate and power down defective cores effectively during manufacturing.
Innovation Solution
Implementing a power isolation infrastructure with power domains that can be disconnected from power supplies, using on-chip power switches and isolation gates to neutralize defects by powering down affected areas and storing defect information in non-volatile memory, allowing the rest of the chip to function while isolating faulty cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional scan testing is used to test all cores, then manufacturing yield decreases due to unnecessary discarding of chips with defective cores, but implementing power isolation infrastructure increases device complexity
Solution Approach 1:
The integrated circuit is divided into multiple power domains, each capable of being independently powered on or off. This segmentation allows defective cores to be isolated by powering down their specific power domain while keeping other domains operational, thereby improving manufacturing yield without requiring complete chip rejection
Solution Approach 2:
Power isolation infrastructure including power switches and isolation gates is integrated into the design before manufacturing. This preliminary action enables automatic isolation of defective cores during testing and operation, preventing the need to discard entire chips and improving yield
2Productivity
If power domains are used to isolate defective cores, then manufacturing yield increases, but test time increases due to multiple testing phases
Solution Approach 1:
The testing process is segmented into internal mode testing and external mode testing phases. Internal mode testing first isolates and tests each power domain independently, then external mode testing tests the interfaces between domains. This segmentation allows efficient identification of defective cores while minimizing overall test time
Solution Approach 2:
The testing approach uses partial action by first testing only the essential internal functionality of each power domain in isolation mode, then performing more comprehensive external interface testing only on passing domains. This reduces total test time while maintaining high yield through selective isolation of defective cores
3Reliability
If scan chains are implemented in each power domain, then defect isolation capability improves, but device complexity increases
Solution Approach 1:
Scan chains are implemented within each power domain to provide localized testing capability. This segmentation allows defects to be isolated to specific domains using domain-specific scan chains, improving reliability without requiring a monolithic scan chain across the entire chip
Solution Approach 2:
The scan chains in each power domain serve multiple functions: testing internal logic within the domain, verifying power domain isolation functionality, and validating interfaces to other domains. This multi-functionality reduces overall device complexity by eliminating the need for separate dedicated test structures
Data Source
AI summary
An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.