Low Profile Power Switching Module With Nested Bus Bars
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Solution Overview
Problem
Current power switching module assemblies face challenges in reducing circuit inductance, particularly as operating frequencies and voltage levels increase, leading to parasitic packaging effects that limit the performance of wide band-gap semiconductor devices.
Innovation Solution
A low inductance packaging solution is achieved through an internal laminated bus structure that overlaps positive and negative bus members with a layer of electrical insulation, extending into the mounting terminal area, which significantly reduces total module inductance and provides minimal parasitic impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonds and planar metal traces are used for signal routing, then manufacturing is simplified and standard footprints are maintained, but circuit inductance increases and parasitic packaging effects worsen
Solution Approach 1:
The patent transitions from planar 2D routing to 3D stacked routing by placing positive and negative bus bars in overlapping layers separated by an insulating layer. This vertical stacking arrangement reduces the current loop area and inductance while maintaining manufacturability through standard lamination processes.
Solution Approach 2:
The patent implements nested bus bar structures where positive and negative bus bars are positioned in overlapping configurations within the same package footprint. The insulating layer allows one bus bar to be effectively nested within the projection of the other, minimizing the enclosed area and reducing parasitic inductance.
2Power
If operating frequency and voltage levels are increased, then power capability is improved, but parasitic packaging effects become more significant and limit performance
Solution Approach 1:
The patent changes the geometric parameters of the bus bar routing by implementing overlapping 3D structures with minimized loop areas. This parameter optimization reduces inductance and parasitic effects, enabling the package to support higher operating frequencies and voltage levels without performance degradation.
3Ease of manufacture
If metal traces are routed on a single layer planar surface, then manufacturing is easier, but inductance is higher due to larger current loop area
Solution Approach 1:
The patent moves from single-layer planar routing to multi-layer stacked routing with vertical overlap. The insulating layer enables this 3D configuration while maintaining manufacturability through standard lamination and bonding processes, reducing the current loop area and associated inductance.
Data Source
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AI summary
A method and system for a power module device is provided. The device includes a base, a circuit board including a plurality of gated switches formed of a semiconductor material, and an electrical bus member configured to connect to a voltage source having a first polarity. The bus member includes a length that is substantially greater than a width of the bus member and the width is substantially greater than a thickness of the bus member. The power module device also includes a second bus member configured to connect to a voltage source having a second polarity. The second bus member is positioned in a nested face-to-face configuration with respect to the first bus member. The power module device further includes a layer of electrical insulation positioned between the first bus member and the second bus member.