Power Tap Cell Layout for Front-to-Backside Power Rail Connection
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and performance degradation due to increased resistance and area requirements of buried power rails, particularly as the technology node scales below 5 nm, where the size and aspect ratio limitations of power rails impact IR drop and frequency supply.
Innovation Solution
The implementation of power tap cells that connect front side power rails to a back side power distribution network, allowing for orthogonal or offset configurations with varying via sizes and aspect ratios, reduces resistance and area usage by integrating power rails into the substrate, eliminating the need for additional routing tracks and enabling further scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are made larger in width to maintain adequate resistance, then power distribution performance is improved, but area usage within the cell increases significantly
Solution Approach 1:
The patent transitions power rail routing from the lateral dimension (within the cell plane) to the vertical dimension (through substrate depth). By routing power rails through deep vias in the substrate and connecting to backside power distribution networks, the solution achieves adequate resistance without consuming excessive lateral area within the cell, effectively moving the problem from 2D to 3D space.
2Reliability
If power rails are increased in aspect ratio to reduce resistance, then power distribution performance is improved, but via resistance increases and capacitance between tracks increases
Solution Approach 1:
The patent implements a nested structure where multiple via levels are stacked vertically to create the power rail connection. Instead of using a single high-aspect-ratio via, the solution uses multiple lower-aspect-ratio vias connected in series through intermediate conductive layers, effectively nesting via structures within each other to achieve the required vertical connection while maintaining acceptable resistance characteristics.
3Productivity
If cell height is scaled down to improve integration density, then miniaturization is achieved, but cell-to-cell space decreases and buried power rail resistance increases
Solution Approach 1:
The patent compensates for the reduced lateral space caused by cell height scaling by utilizing the vertical dimension. Power rails are routed through deep vias that extend vertically through the substrate to reach backside power distribution networks, allowing adequate power rail dimensions to be maintained in the vertical direction even as lateral cell dimensions are reduced for higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in transistors with reduced power consumption, improved performance, and lower manufacturing costs, while enhancing IR drop and area efficiency in semiconductor designs, addressing the limitations of traditional power rail configurations.
Implementation Method 1
one or more power vias connecting the first power rail to the second power rail
Data Source
AI summary
A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.