Processor Power Throttle Unit for Instruction Issue Rate Control
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Solution Overview
Problem
The increasing power consumption in mobile devices due to high-density integrated circuits and complex instruction sets leads to reduced battery life and potential thermal issues, as existing methods to manage peak power dissipation often result in unacceptable performance reductions.
Innovation Solution
A power throttle unit within the processor pipeline stage monitors and limits the issue rate of high-power instructions, such as SIMD instructions, based on power state estimation and user-defined settings, to maintain optimal power consumption within thermal design limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If issue rate of high-power instructions is limited to reduce power consumption, then power consumption is reduced, but overall performance deteriorates
Solution Approach 1:
The patent segments the instruction stream by identifying and separately controlling high-power instructions (such as SIMD instructions) from normal instructions. A power throttle unit is introduced that specifically targets and limits the issue rate of identified high-power instruction types, while allowing other instructions to proceed without restriction. This selective segmentation approach reduces power consumption by focusing throttling only on problematic instruction types rather than applying blanket limitations to all instructions, thereby minimizing the impact on overall performance.
Solution Approach 2:
The patent applies local quality by implementing differential treatment of different instruction types based on their power consumption characteristics. High-power instructions like SIMD operations are subject to issue rate limiting through the power throttle unit, while low-power instructions are not affected. This localized application of throttling ensures that power reduction measures are applied precisely where needed (to high-power instructions) without degrading the execution of other instructions, thus resolving the contradiction between power reduction and performance maintenance.
2Power
If simple instruction issue limitation is applied to manage peak power dissipation, then power dissipation is controlled, but performance reduction becomes unacceptable
Solution Approach 1:
The patent implements dynamic control through the power throttle unit that operates within the processor pipeline stage. The throttle unit dynamically monitors and adjusts the issue rate of high-power instructions based on current power conditions and instruction type identification. This dynamic approach allows the system to adaptively control peak power dissipation in real-time by selectively limiting only those instructions that would cause power spikes, rather than applying static or blanket issue limitations that would unnecessarily reduce overall performance.
Solution Approach 2:
The patent employs feedback mechanisms through the power throttle unit that receives information about instruction types and power dissipation levels. The throttle unit uses this feedback to make real-time decisions about which instructions to limit, enabling precise control over peak power dissipation. This feedback-driven selective throttling ensures that performance is maintained by only limiting instructions that would otherwise cause power management issues, rather than applying broad performance-reducing limitations.
Data Source
AI summary
A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.