Hierarchical Power Throttling Circuit Synchronization for Voltage Stability
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Solution Overview
Problem
Conventional power management systems in processor-based systems face challenges in efficiently managing power distribution and throttling to prevent voltage droops and excess heat generation, particularly due to sudden current demand spikes, which can affect performance and exceed power and thermal limits.
Innovation Solution
A hierarchical power management system with local area management (LAM) and centralized power estimation and limiting (PEL) circuits, synchronized through a master clock signal, monitors and throttles power consumption by estimating current demand and generating time-based power events to maintain performance within power and thermal limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power consumption is increased to maintain high performance, then processing speed and computational capability are improved, but voltage droops and thermal issues occur exceeding power and thermal limits
Solution Approach 1:
The power management system is divided into multiple hierarchical levels: local area management (LAM) circuits at the cluster level and a centralized power estimation and limiting (PEL) circuit at the system level. This segmentation allows localized power monitoring and throttling at LAM circuits while the PEL circuit provides overall system power management, enabling fine-grained control to prevent voltage droops during high-performance operation.
Solution Approach 2:
The system performs preliminary power estimation and throttling decisions before voltage droops occur. The LAM circuits continuously monitor power consumption and proactively throttle local devices when approaching power limits, while the PEL circuit estimates overall system power usage and preemptively adjusts power allocation, preventing voltage instability before it occurs.
2Reliability
If centralized power management is used to control overall power consumption, then power and thermal limits are maintained, but response time to sudden current demand spikes increases
Solution Approach 1:
The hierarchical segmentation enables LAM circuits to handle local power management independently, providing fast local response to current demand spikes without waiting for centralized PEL circuit decisions. The PEL circuit maintains overall power limit compliance while allowing LAM circuits to respond rapidly to local conditions, resolving the contradiction between centralized control and fast response.
Solution Approach 2:
The system implements feedback loops at both LAM and PEL levels. LAM circuits receive real-time feedback on local power consumption and immediately adjust throttling accordingly, while the PEL circuit receives feedback from LAM circuits and adjusts overall power allocation. This multi-level feedback mechanism enables rapid response to current demand spikes while maintaining power limit compliance.
3Reliability
If power throttling is applied to prevent voltage droops, then voltage stability is maintained, but system performance and processing throughput decrease
Solution Approach 1:
Power throttling is applied locally at LAM circuits only to specific devices or clusters that are causing power issues, rather than uniformly across the entire system. This allows other devices to continue operating at full performance, maintaining overall system throughput while ensuring voltage stability through targeted local throttling.
Solution Approach 2:
The power management system dynamically adjusts throttling levels based on real-time power consumption and voltage conditions. Rather than applying fixed throttling, the LAM and PEL circuits continuously monitor system state and adjust power allocation dynamically, maintaining voltage stability while maximizing processing throughput under current conditions.
Data Source
AI summary
Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.