Power Throttling for Multicore ML Chips
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Solution Overview
Problem
Multicore systems experience sudden power surges when cores transition from idle to operational mode, exceeding maximum power limits due to slow response times of conventional current sensors, which can violate PCI specifications.
Innovation Solution
A system and method for power throttling that monitors the current and current slew rate on the main power rail, triggering a throttling signal when thresholds are exceeded, allowing the power throttling module to manage power consumption by lowering clock frequency or disabling cores, with user-definable thresholds and programmable duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional current sensors are used to monitor power consumption, then the system can detect power usage, but the response time is too slow (100 microseconds) causing violation of maximum power limits and PCI specifications
Solution Approach 1:
The patent introduces an intermediary current sensor positioned between the power source and the multicore system that specifically monitors the main power rail current. This intermediary sensor enables direct measurement of power consumption with fast response time, solving the problem of slow detection while maintaining accuracy.
Solution Approach 2:
The patent replaces the conventional slow-response current sensing mechanism with a high-speed current detection system that can respond in nanoseconds. This substitution of the measurement system enables real-time detection of power surges before they violate maximum power limits or PCI specifications.
2Power
If bulk capacitors are added to supplement power during transitions, then power availability increases, but the capacitor type selection is limited by chip design implementation
Solution Approach 1:
The patent implements dynamic power management that adapts to different power scenarios. The system dynamically adjusts power delivery by controlling clock frequency and enabling/disabling cores based on real-time power consumption monitoring, providing flexibility without requiring specific capacitor implementations.
Solution Approach 2:
The patent changes operational parameters (clock frequency, core enablement) to manage power consumption dynamically. By adjusting these parameters rather than relying on fixed capacitor configurations, the system achieves power management flexibility that is independent of chip design constraints.
3Productivity
If cores transition from idle to full operation simultaneously, then processing capability increases, but sudden power surge occurs exceeding maximum power limits
Solution Approach 1:
The patent implements preliminary action by monitoring current consumption before full operation begins. The system detects when cores are transitioning from idle state and preemptively takes throttling action to prevent power surges, allowing productive operation while maintaining power within limits.
Solution Approach 2:
The patent establishes a feedback mechanism where the current sensor continuously monitors power consumption and feeds this information back to the power management system. When power consumption approaches maximum limits during core transitions, the system receives feedback and automatically throttles power delivery to prevent exceeding maximum power limits.
Data Source
AI summary
A system includes a multicore chip configured to perform machine learning (ML) operations. The system also includes a power monitoring module configured to measure power consumption of the multicore chip on a main power rail of the multicore chip. The power monitoring module is further configured to assert a signal in response to the measured power consumption exceeding a first threshold. The power monitoring module is further configured to transmit the asserted signal to a power throttling module to initiate a power throttling for the multicore chip.