Hierarchical Power Throttling Circuits With Time-Synced Event Reporting
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Solution Overview
Problem
Conventional power management systems in processor-based systems face challenges in efficiently managing power distribution and throttling to prevent voltage droops and excess heat generation due to varying workload conditions, which can exceed maximum current limitations and impact performance.
Innovation Solution
A hierarchical power management system with local area management (LAM) and centralized power estimation and limiting (PEL) circuits, synchronized through a master clock signal, to monitor and throttle power consumption by sampling activity at defined time windows, generating synchronized power events, and adjusting power levels and performance to meet overall power and thermal limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power consumption is increased to meet higher workload demands, then processing performance is improved, but voltage droops and heat generation occur exceeding power and thermal limits
Solution Approach 1:
The power management system is divided into multiple hierarchical levels: local area management (LAM) circuits that monitor and report power events at individual processing device levels, regional management circuits that aggregate events from multiple LAM circuits, and a centralized power estimation and limiting (PEL) circuit that makes final throttling decisions. This segmentation allows localized power monitoring and reporting while maintaining centralized control, enabling the system to respond to power violations at the appropriate granularity without requiring complete system-wide coordination for every event.
Solution Approach 2:
The system performs preliminary actions by establishing time synchronization across all LAM and regional circuits before power event monitoring begins. A master clock circuit generates synchronized time windows that are distributed to all subordinate circuits, ensuring that power sampling and event reporting occur at predetermined, coordinated intervals. This preliminary synchronization prevents timing mismatches that could lead to inaccurate power event detection and ensures consistent power limit enforcement across the hierarchical structure.
2Device complexity
If power sampling and event reporting are performed without time synchronization between hierarchical circuits, then device complexity is reduced, but measurement precision and reliability of power event detection deteriorate
Solution Approach 1:
The hierarchical power management system implements feedback mechanisms at multiple levels. LAM circuits monitor power consumption of individual processing devices and generate power events when thresholds are exceeded. These events are reported to regional circuits, which aggregate events from multiple LAM circuits and forward them to the centralized PEL circuit. The PEL circuit receives these feedback events, determines whether power limits are violated, and generates power limiting management responses that are propagated back down the hierarchy to throttle processing devices. This multi-level feedback loop ensures accurate power event detection and appropriate corrective action while maintaining manageable complexity through distributed monitoring.
Solution Approach 2:
The time synchronization mechanism serves multiple functions simultaneously: it coordinates power sampling intervals across all LAM and regional circuits, synchronizes power event reporting timestamps, enables accurate time-stamping of power events for debugging and analysis, and provides a common reference framework for the entire hierarchical power management system. This universal synchronization approach, implemented through a master clock distributing time windows to all subordinate circuits, achieves precise measurement without requiring complex individual timing circuits at each node.
Data Source
AI summary
Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.