Power Transistor Package With Dual-Side Load Terminals
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Solution Overview
Problem
The resistance of internal package interconnects in power transistor chip packages remains constant despite decreasing R DS(on) values of semiconductor transistor chips, impacting overall device efficiency and increasing costs due to fixed chip size requirements.
Innovation Solution
A power transistor chip package design featuring a power transistor chip with dual side load terminals and a symmetric encapsulation body, where both sides of the encapsulation body have package load terminals connected directly to the chip's load electrodes, reducing electrical resistance and allowing for increased current carrying capacity and improved circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the chip size is reduced to lower cost, then manufacturing cost decreases, but the internal package interconnect resistance becomes a larger proportion of the total R DS(on) value, degrading overall device performance
Solution Approach 1:
The patent transitions from a conventional single-side load terminal configuration to a dual-side load terminal configuration. By placing load terminals on both the front and back sides of the chip, the current path is shortened and resistance is reduced, allowing smaller chip sizes without performance degradation.
Solution Approach 2:
The load terminal function is segmented across multiple locations - front side load terminals and back side load terminals. This segmentation distributes the current flow paths, reducing the resistance contribution from internal interconnects while maintaining the electrical connection function.
2Device complexity
If conventional single-side load terminal configuration is used, then device structure is simple, but the internal package interconnect resistance contributes significantly to total R DS(on) value
Solution Approach 1:
The patent adds spatial dimension to the terminal configuration by utilizing both front and back sides of the chip for load terminals. This three-dimensional arrangement reduces current path length and resistance without significantly increasing structural complexity.
Solution Approach 2:
The patent merges the load terminal function across multiple surfaces and locations. By combining front side load terminals with back side load terminals, the overall resistance is reduced while maintaining a relatively integrated package structure.
Data Source
Figure 1A~3
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AI summary
A power transistor chip package (100A, 100B) includes a power transistor chip (120). The power transistor chip includes a first load electrode (122) on a first side (120_1), a second load electrode (124) on a second side (120_2) opposite the first side and a control electrode. The power transistor chip package further includes a chip pad (140) on which the power transistor chip is disposed. The first side faces the chip pad and the first load electrode is electrically connected to the chip pad. An encapsulation body (160) encapsulates the power transistor chip. The encapsulation body includes a footprint side(160F), a top side (160T) opposite the footprint side and side faces extending between the footprint side and the top side. The power transistor chip package further includes a first package load terminal electrically connected to the first load electrode of the power transistor chip, part I and part II second package load terminals (184_1, 184_2) both electrically connected directly to the second load electrode of the power transistor chip and a package control terminal electrically connected to the control electrode of the power transistor chip. The part I and part II second package load terminals are aligned with opposite sides faces of the encapsulation body.