Power Transistor Arrangement with Flip-Chip Cascade
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Solution Overview
Problem
Power semiconductor chips integrated into electronic packages face significant inductivity issues with discrete components and thermal limitations with chip-on-chip structures, leading to high switching losses and thermal constraints.
Innovation Solution
A power transistor arrangement featuring a carrier with two power transistors, where the control electrodes face the carrier, and their power electrodes are electrically coupled via a low-thermal-resistance conductive structure, forming a flipchip cascade arrangement that minimizes inductivity and thermal limitations, allowing for efficient heat dissipation and reduced switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete components or packages are used for power transistors, then ease of manufacture is improved, but package inductivity increases leading to switching losses
Solution Approach 1:
The patent merges multiple power transistors onto a single semiconductor substrate, creating an integrated power transistor arrangement. This consolidation reduces the number of discrete components and interconnections, thereby lowering package inductivity and switching losses while maintaining manufacturing efficiency through standardized integration processes.
Solution Approach 2:
The patent transitions from planar discrete component layout to a three-dimensional integrated structure where power transistors are vertically stacked or closely arranged on the substrate. This dimensional reorganization minimizes current path lengths and parasitic inductance, reducing switching losses without compromising ease of manufacture.
2Loss of energy
If chip-on-chip structure is used for power transistors, then package inductivity is reduced, but thermal limitations occur leading to heat dissipation issues
Solution Approach 1:
The patent introduces an intermediate heat dissipation structure between the power transistor chips and the substrate, such as thermal vias or heat spreaders. This intermediary element efficiently conducts heat away from the transistor junctions while maintaining the low-inductivity chip-on-chip configuration, thus resolving thermal limitations without increasing switching losses.
Solution Approach 2:
The patent employs multiple identical power transistor units arranged in parallel on the substrate, each with its own thermal management path. This replication allows heat to be distributed across multiple thermal channels, preventing thermal concentration and maintaining effective heat dissipation while preserving the low-inductivity integrated structure.
3Ease of operation
If control electrodes face away from the carrier in conventional arrangements, then ease of connection is improved, but package inductivity increases
Solution Approach 1:
The patent inverts the conventional orientation by having control electrodes face towards the carrier substrate rather than away from it. This inversion allows control signals to be transmitted through low-inductivity vias or traces in the substrate, significantly reducing package inductivity and switching losses while maintaining ease of connection through standardized substrate bonding processes.
Data Source
AI summary
Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier.