Power Transistor Gate Driver for Fast Turn-Off and Lower EMI
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Solution Overview
Problem
Existing driver circuits for power transistors face challenges in reducing electromagnetic interference (EMI) while maintaining fast switching times, as increased switching speed leads to higher EMI levels and power dissipation, and conventional constant current source techniques result in high power-off delays.
Innovation Solution
A driver circuit with control circuitry that includes a sample and hold circuit, gate discharge circuit, and voltage differentiator to quickly reach the Miller zone, allowing for controlled voltage slope at the drain terminal and optimized current absorption, and compensation for threshold voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching speed is increased to reduce power dissipation, then power dissipation is reduced, but electromagnetic interference level increases
Solution Approach 1:
The patent applies dynamics by making the gate current adjustable and variable rather than fixed. The driver stage can dynamically modify the gate current waveform to optimize switching performance, allowing the system to adapt between fast switching (lower power dissipation) and controlled switching (lower EMI) based on operational requirements
Solution Approach 2:
The patent changes the parameter of gate current characteristics (waveform shape, amplitude, duration) to control the switching behavior. By modifying these parameters, the driver can achieve fast switching to reduce power dissipation while controlling the voltage slopes to limit electromagnetic interference generation
2Stability of the object's composition
If constant current source is used to control voltage slope, then voltage slope is controlled, but power-off delay increases
Solution Approach 1:
The patent replaces the static constant current source with a dynamic driver stage that can adjust gate current in real-time. This allows the system to provide controlled voltage slopes during switching while maintaining fast power-off response, eliminating the delay associated with fixed constant current sources
Solution Approach 2:
The driver stage employs periodic or pulsed gate current waveforms to control the switching transitions. By applying current in controlled pulses rather than continuous constant current, the system achieves voltage slope control during switching while enabling rapid turn-off when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces delays in discharging gate capacitance, minimizes EMI, and ensures fast switching times by controlling the voltage slope and current absorption, thereby optimizing power consumption and reducing power-off delays.
Implementation Method 1
a voltage differentiator to detect changes in the voltage between the gate terminal and the source terminal
Implementation Method 2
a sample and hold circuit to store a value representative of the voltage between the gate terminal and the source terminal when the power transistor operates in the saturation region
Implementation Method 3
a gate discharge circuit to quickly discharge the capacitance of the gate terminal of the power transistor
Data Source
AI summary
An apparatus and a method switch a load through a power transistor. The apparatus includes: a first current generator for generating a current to charge a capacitance of a control terminal of the power transistor during power on of the power transistor; a second current generator for generating a current to discharge the capacitance during power off of the power transistor. The apparatus is equipped with control circuitry having a storage element for storing a voltage value representative of the potential difference between the control terminal and a conduction terminal of the power transistor when the power transistor operates in the saturation region and a discharge circuit for generating an additional current to discharge the capacitance during the power-off process. The additional current is a function of the potential difference of the control terminal and the stored voltage value from the conduction terminal.