Power Transistor Arrangement with Isolated Carrier Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor chips face significant inductivity-related switching losses in discrete component packages and thermal limitations in chip-on-chip structures, particularly for silicon field effect transistor chips.
Innovation Solution
A power transistor arrangement featuring a carrier with electrically isolated main and terminal regions, where power transistors are strategically positioned and coupled to minimize inductance and thermal resistance, utilizing a leadframe structure and conductive coupling to form a low-inductive package suitable for power applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete components or packages are used to implement power semiconductor circuits, then ease of manufacture and circuit implementation are improved, but package inductivity increases significantly leading to switching losses
Solution Approach 1:
The patent merges multiple discrete power semiconductor components into a single integrated power semiconductor device with multiple terminals. The device integrates first and second power electrodes, control electrodes, and multiple terminals (first, second, third, and fourth terminals) into one unified structure, eliminating the need for separate discrete components and their associated interconnections. This integration directly reduces package inductivity and switching losses while maintaining ease of manufacture.
Solution Approach 2:
The patent employs a three-dimensional terminal arrangement with terminals extending in multiple directions and planes. The first and second terminals are arranged in a first plane, while the third and fourth terminals are arranged in a second plane, creating a multi-dimensional electrical connection structure. This spatial arrangement minimizes current path lengths and reduces package inductivity, thereby reducing switching losses while maintaining manufacturability.
2Loss of energy
If chip-on-chip structure is used to implement cascade or half bridge circuits, then package inductivity is reduced, but thermal limitations occur particularly for silicon field effect transistor chips
Solution Approach 1:
The patent segments the power semiconductor device into distinct functional regions with separate thermal management paths. The device includes a first power electrode and a second power electrode that are electrically isolated and thermally separable, allowing independent heat dissipation pathways. This segmentation enables efficient thermal management while maintaining the low-inductivity integrated structure.
Solution Approach 2:
The patent introduces intermediate thermal management structures including a first heat dissipation element associated with the first power electrode and a second heat dissipation element associated with the second power electrode. These intermediary thermal management components facilitate efficient heat transfer from the power electrodes to the environment, resolving thermal limitations while maintaining the integrated low-inductivity design.
Data Source
AI summary
Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.