Power Transistor Trench Layout With Lattice-Aligned Sidewalls
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Solution Overview
Problem
Existing transistor devices for power applications face challenges in achieving consistent performance due to variations in contacting source and body regions, which can lead to processing inconsistencies.
Innovation Solution
The fabrication process involves forming trenches in the semiconductor body with sidewalls aligned to specific lattice planes of the semiconductor material, using an etchant with selective etch rates to ensure consistent sidewall angles, allowing for precise alignment and reduced fluctuations in performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form trenches, then the manufacturing process is simple, but the sidewall alignment and distance consistency between trenches vary, leading to performance fluctuations
Solution Approach 1:
The patent changes the etching parameters by using anisotropic etching with specific etch rates that depend on lattice planes. This causes certain crystal planes to etch slower than others, automatically forming sidewalls aligned with slow-etching lattice planes and achieving consistent sidewall angles and trench distances without complex process control
Solution Approach 2:
The etching process self-regulates the sidewall formation by exploiting the inherent anisotropic etch rates of different lattice planes. The slow-etching planes naturally become the sidewalls, and the process automatically maintains consistent geometry without requiring external alignment controls or complex process intervention
2Reliability
If contact holes are formed with high precision alignment, then the performance is consistent, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The lattice-plane-aligned trenches self-establish the correct geometric relationships and positions. Subsequent contact holes automatically align with the trenches through the self-aligned process, eliminating the need for separate high-precision alignment steps and reducing manufacturing time while maintaining performance consistency
Solution Approach 2:
The trenches are pre-formed with sidewalls aligned to lattice planes before contact hole formation. This preliminary alignment creates a self-aligned reference structure that guides subsequent contact hole placement, ensuring consistent positioning without requiring additional alignment operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform performance across transistor cells by maintaining consistent distances between trenches, reducing processing variations, and enabling misaligned contact holes without affecting performance.
Implementation Method 1
etching the semiconductor body with an etchant that comprises an etch rate which depends on lattice planes of the semiconductor material such that a first lattice plane of the semiconductor body forms a first sidewall of the second trench
Data Source
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Figure 3A
AI summary
A semiconductor device comprises a semiconductor body having a first major surface. The semiconductor body comprises a source region of a first conductivity type, a body region of a second conductivity type, and a drift region of the first conductivity type. A first trench extends from the first major surface of the semiconductor body into the semiconductor body along a first direction. A first gate electrode is located in the first trench. A second trench extends from the first major surface of the semiconductor body into the semiconductor body. A conductive material is located in the second trench. The conductive material is in electrical contact with the source region and the body region of the semiconductor body. A first sidewall of the second trench corresponds to a first lattice plane of the semiconductor body.