Power Semiconductor Unit Layout for Low-Inductance Parallel Loops
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Solution Overview
Problem
Conventional power semiconductor single-tube devices have high parasitic inductance due to pin connections, which increases circuit complexity, restricts heat dissipation, and makes parallel connections difficult.
Innovation Solution
A power semiconductor integrated unit with a substrate and flexible printed circuit board, eliminating pins and bonding wires, allowing direct surface-mount connections, and featuring a geometric design for low parasitic inductance and symmetrical layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pins are used for electrical connection in conventional packages, then the device can be connected to the printed circuit board, but the parasitic inductance is significantly increased and the placement is restricted
Solution Approach 1:
The patent removes the pin structure from the package completely. The power semiconductor device is directly mounted on the printed circuit board with its electrodes exposed on the board surface, eliminating the need for pins that penetrate through the board. This extraction of the pin element resolves the contradiction by providing electrical connection without the associated parasitic inductance and placement restrictions.
Solution Approach 2:
The patent transitions from a three-dimensional pin penetration connection to a two-dimensional surface-mounted connection. The electrodes are connected to the printed circuit board in the same plane rather than through vertical pin penetration, changing the connection dimension from depth-oriented to surface-oriented. This dimensional change eliminates the need for vertical conductor paths and reduces parasitic inductance.
2Reliability
If pins penetrate all layers of the printed circuit board, then electrical connection is achieved, but the conductor layout must bypass the pin horizontally increasing parasitic inductance
Solution Approach 1:
The pin structure that causes the harmful bypass path is completely removed. The power semiconductor electrodes are directly connected to the printed circuit board surface, eliminating the vertical pin penetration that forces conductors to take horizontal bypass paths. This extraction eliminates the source of the parasitic inductance problem.
3Device complexity
If a conventional single-tube package is used without outward insulation, then the structure is simple, but a heat sink cannot be directly attached and an insulating film must be added reducing thermal conductivity
Solution Approach 1:
The printed circuit board serves as an intermediary that provides both electrical connection and thermal conduction pathways. The power semiconductor is mounted directly on the PCB with electrodes exposed on the surface, allowing the PCB itself to act as the thermal path to heat sinks without requiring additional insulating films. The PCB's ground layers and power layers provide low-resistance thermal conduction paths.
Solution Approach 2:
The printed circuit board performs multiple functions simultaneously: it provides electrical connection for the power semiconductor electrodes, serves as a thermal conduction path to heat sinks, and acts as a mechanical mounting substrate. This multi-functionality eliminates the need for separate insulating films and dedicated thermal pathways.
4Quantity of substance
If pins are used in conventional packages, then single-tube devices can be connected, but parallel connection of multiple tubes is difficult due to inconsistent circuit length and asymmetrical layouts
Solution Approach 1:
The patent segments the connection structure into modular electrode contacts on the printed circuit board surface. Each power semiconductor device connects to its own dedicated electrode contacts, and multiple devices can be arranged in symmetrical patterns around a central point. This segmentation allows independent optimization of each device's connection path length, enabling consistent circuit lengths for parallel connections.
Solution Approach 2:
The patent uses symmetrical arrangement of multiple power semiconductor devices around a central mounting point on the printed circuit board. By positioning devices symmetrically and routing their connection paths through equivalent PCB layers and traces, the design achieves consistent circuit lengths despite the physical asymmetry of individual device placements. This symmetrical design strategy enables precise matching of parasitic inductances for parallel-connected devices.
Data Source
AI summary
A power semiconductor integrated unit including a substrate with a recess to accommodate a power semiconductor chip, and top surfaces of a source lower-surface pad and a gate pad that are on the same side surface of the power semiconductor chip are or nearly flush with a top surface of a base plate. A flexible printed circuit board connects to the substrate and power semiconductor chip, the flexible printed circuit board has source and gate conductive traces, the source conductive trace connects to the source lower-surface pad on a top side of the chip, and the gate conductive trace connects to the gate pad on the top side of the chip. The flexible printed circuit board has an epitaxial portion, and the gate conductive trace and the source conductive trace extend onto the epitaxial portion. The integrated unit also includes a power converter circuit structure and a parallel loop structure.