Power-Up Self-Calibration Circuit for Chip Parameter Offset
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Solution Overview
Problem
Current chip parameter burn-in and adjustment methods, especially during the wafer and chip levels, face issues with accuracy due to measurement deviations and parasitic effects, leading to poor chip performance and increased costs.
Innovation Solution
A self-calibration circuit and method that includes a counting circuit, calibration data latch circuit, calibration data selection circuit, and parameter calibration circuit, which automatically calibrate chip parameters upon power-up, eliminating the need for special processes and reducing costs by integrating self-detection and calibration functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If wafer level parameter burn-in and adjustment method is used, then the process is simple and does not require detection circuit, but the number of pads needed increases and fuse must be employed
Solution Approach 1:
The chip performs self-calibration using internal circuits (counting circuit, latch circuit, selection circuit, and calibration circuit) without requiring external detection circuits or fuse operations. The calibration data is stored and applied automatically during chip operation, eliminating the need for external pad connections for calibration purposes.
2Quantity of substance
If wafer level parameter burn-in and adjustment method with detection circuit is used, then the number of pads is reduced, but additional detection circuit is required which increases power consumption
Solution Approach 1:
The chip performs self-calibration using internal circuits (counting circuit, latch circuit, selection circuit, and calibration circuit) without requiring external detection circuits or fuse operations. The calibration data is stored and applied automatically during chip operation, eliminating the need for external pad connections for calibration purposes.
3Manufacturing precision
If OTP or memory burn-in and adjustment method is used, then parameter adjustment can be achieved, but special process and high design capacity are required leading to high cost
Solution Approach 1:
The patent uses standard CMOS process to implement the calibration circuits and storage elements, replacing expensive OTP or memory-based solutions. The calibration data is stored in simple latch circuits and flip-flops that can be implemented using standard cell libraries, significantly reducing manufacturing cost and process complexity while maintaining calibration precision.
4Ease of manufacture
If protocol burn-in and adjustment method is used, then no special process is required, but detection circuit, fuse, large-size switch tubes and protocol circuit are required increasing circuit cost
Solution Approach 1:
The patent extracts and eliminates the protocol circuit and fuse components from the calibration system. The calibration is performed directly through internal circuits using counting sequences and latch storage, removing the need for external protocol handling and fuse-based programming while reducing overall circuit complexity.
Solution Approach 2:
The chip performs self-calibration using internal circuits (counting circuit, latch circuit, selection circuit, and calibration circuit) without requiring external detection circuits or fuse operations. The calibration data is stored and applied automatically during chip operation, eliminating the need for external pad connections for calibration purposes.
5Productivity
If parameter burn-in and adjustment is performed during wafer level, then packaging can be completed, but measurement deviation due to needle piercing force and test environment occurs
Solution Approach 1:
The patent performs calibration during chip-level testing before packaging, allowing measurement and adjustment to occur under controlled test conditions without the interference of packaging-induced parameter changes. The calibration data captured at this stage accounts for the chip's actual electrical characteristics before being enclosed in packaging.
6Manufacturing precision
If parameter burn-in and adjustment is performed during chip level, then packaging-induced parameter dispersion is corrected, but PCB parasitic causes errors during system operation
Solution Approach 1:
The chip performs self-calibration during system operation using internal circuits (counting circuit, latch circuit, selection circuit, and calibration circuit). The calibration compensates for PCB parasitic effects by measuring and adjusting parameters in-situ during actual operation, ensuring accuracy despite external environmental factors.
Solution Approach 2:
The patent implements dynamic calibration that can be performed at multiple stages (chip level before packaging and system level during operation). The calibration process adapts to different operational conditions, allowing the system to correct for PCB parasitic effects and other environmental factors that arise during actual system operation.
Data Source
AI summary
A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement. Thus, a parameter calibration with a higher accuracy and flexibility is realized in a cheaper way.