Power-Up Signal Circuit for Fast DPD Wake-Up

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Solution Overview

Problem

Conventional power-up signal generating circuits in integrated circuits experience delays in activating the power-up signal when transitioning from deep power down (DPD) mode to normal operation mode, leading to inefficiencies in current consumption and circuit area usage.

Innovation Solution

A power-up signal generating circuit with a detecting unit that outputs a bias signal corresponding to the external power voltage and a signal generating unit that generates a power-up signal with a logic level matching the external power voltage, allowing the internal voltage to reach a predetermined level after a specific time and maintain a ground voltage level during inactivation, thereby reducing leakage current and optimizing circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the power-up signal generating circuit uses a conventional detecting unit with voltage drop elements and capacitors, then the circuit can generate a bias signal corresponding to external power voltage, but the power-up signal activation is delayed when transitioning from deep power down mode to normal operation mode

Engineering Contradiction:
Improvepower-up signal activation speedVSAvoiddelay time in mode transition
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent extracts and removes the capacitor component from the conventional detecting unit configuration. By eliminating the capacitor that causes charging delays, the circuit achieves immediate response when transitioning from DPD mode to normal operation mode, resolving the activation delay problem while maintaining the voltage detection functionality through the remaining resistor-based voltage division network.

Inventive Principle:
Principle #2Taking out (Extraction)

2Speed

If the power-up signal generating circuit activates the power-up signal immediately without delay, then the response speed of internal circuits is improved, but transistor leakage current increases during deep power down mode

Engineering Contradiction:
Improveresponse speed of internal circuitsVSAvoidtransistor leakage current
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent implements dynamic control of the detecting unit through the DPD signal. The circuit configuration changes based on the power mode: in DPD mode, the detecting unit is configured to minimize leakage current; in normal operation mode, it provides immediate power-up signal activation. This dynamic reconfiguration resolves the contradiction between fast response and low leakage by adapting the circuit behavior to the current operational state.

Inventive Principle:
Principle #15Dynamics

3Reliability

If the conventional detecting unit uses multiple voltage drop elements and capacitors, then the circuit can provide voltage division functionality, but the circuit area occupied increases

Engineering Contradiction:
Improvevoltage level detection accuracyVSAvoidcircuit area occupied by detecting unit
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes unnecessary components (capacitors and excess voltage drop elements) from the conventional detecting unit while retaining the essential voltage division functionality through a simplified resistor network. This extraction reduces the circuit area significantly while maintaining the ability to accurately detect voltage levels and generate the appropriate bias signal for power-up signal generation.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7990189B2Power-up signal generating circuit and integrated circuit using the same
Publication Date: 2011.08.02 SK HYNIX INC
  • US7990189B2 patent drawing
  • US7990189B2 patent drawing
  • US7990189B2 patent drawing

AI summary

A power-up signal generating circuit includes a detecting unit configured to output a bias signal having a voltage level corresponding to an external power voltage in response to an internal voltage and a deep power down (DPD) signal; and a signal generating unit configured to generate a power-up signal having a logic level corresponding to the voltage level of the external power voltage in response to the DPD signal and the bias signal, wherein the internal voltage increases during an activation time of the power-up signal to reach a predetermined voltage level after a predetermined time, and maintains a ground voltage level during an inactivation period of the power-up signal.