Power-Up Signal Circuit With Feedback to Prevent Latch-Up
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Solution Overview
Problem
Conventional power-up signal generation circuits in semiconductor devices can lead to latch-up phenomena and unintended initialization due to direct supply of external power voltage before reaching the target level, causing potential damage and operational instability.
Innovation Solution
A power-up signal generation circuit that includes a control signal generation unit, a level tracing voltage generation unit, and a power-up signal generation unit, which adjust the level tracing voltage and target voltage levels to stabilize the power-up signal, preventing initialization and ensuring reliable operation by generating a power-up signal only when the external power voltage sufficiently rises.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the external power voltage VDD is directly supplied to the internal circuit before reaching the target level, then the power-up time is reduced, but a latch-up phenomenon occurs causing potential damage
Solution Approach 1:
The power-up signal generation circuit performs preliminary detection of the external power voltage VDD level before allowing it to supply to the internal circuit. The circuit detects when VDD reaches the target level V_TARGET and generates a power-up signal PWRUP only at that point, preventing premature power supply that would cause latch-up phenomena while avoiding unnecessary delay.
2Reliability
If the external power voltage VDD is supplied only after reaching the target level, then the latch-up phenomenon is prevented, but the power-up time increases
Solution Approach 1:
The power-up signal generation circuit continuously monitors the external power voltage VDD and provides feedback control. When VDD reaches V_TARGET, the circuit generates PWRUP to enable internal circuit operation. This feedback mechanism ensures the circuit starts only when voltage conditions are met, preventing latch-up while minimizing delay through real-time monitoring.
3Reliability
If the power-up signal is generated when VDD reaches the target level, then the internal circuit operates stably, but voltage drops during active operations cause unintended initialization
Solution Approach 1:
The circuit performs preliminary setup by generating the power-up signal PWRUP only when VDD reaches V_TARGET, ensuring stable initial operation. The detection voltage V_DET is preliminarily established at an appropriate level (e.g., VDD/2 through resistive division) to create a stable reference that prevents unintended resets during subsequent voltage fluctuations from active operations.
4Loss of time
If the detection voltage level is set low to enable early power-up, then the power-up time is reduced, but the circuit becomes sensitive to voltage drops causing false resets
Solution Approach 1:
The circuit changes the detection voltage parameter V_DET to an appropriate level that balances early power-up with stability. By setting V_DET at a suitable threshold (such as through resistive division to achieve VDD/2), the circuit enables power-up sufficiently early to minimize delay while maintaining enough margin to tolerate normal voltage drops during active operations without triggering false resets.
Data Source
AI summary
A power-up signal generation circuit includes a control signal generation unit suitable for generating first and second control voltages based on a power-up signal, a level tracing voltage generation unit suitable for generating a level tracing voltage whose voltage level varies based on the first and second control voltages, and a power-up signal generation unit suitable for generating the power-up signal based on the level tracing voltage, and providing a feedback on the power-up signal to the control signal generation unit.