Power-Up Header Circuitry for Multi-Bank Memory Leakage Control
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Solution Overview
Problem
Current memory designs for L1/L2 caches do not support efficient power-gating schemes, leading to inefficiencies in leakage power management, which is critical as leakage power consumption becomes comparable to dynamic power in high-performance Systems-on-Chip (SoC) with technology scaling.
Innovation Solution
The implementation of a fine-grain automatic power management scheme using a power-up header technique for multi-bank memory applications, which selectively powers up memory cores and wordline drivers before access using retention signals and bank addresses, allowing for fine-grained power-gating control and automatic power-down of unselected banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional memory layout techniques are used, then memory performance is maintained, but leakage power consumption increases
Solution Approach 1:
The memory array is divided into multiple independently power-gatable banks. Each bank can be individually powered down when not in use, allowing selective power management at the bank level rather than requiring power gating of the entire memory array, thus maintaining performance of active banks while reducing leakage in inactive banks.
Solution Approach 2:
Different power management strategies are applied to different regions of the memory array. Specifically, power gating is applied at the bank level based on local access patterns, allowing each bank to have its power state optimized independently according to its specific usage requirements rather than applying a uniform power management approach.
2Loss of energy
If power-gating is applied to reduce static power, then leakage power is reduced, but memory access delay increases due to wake-up time
Solution Approach 1:
Power gating control circuitry is pre-configured with bank address information to predict which banks will be accessed next. This allows the system to proactively power up anticipated banks before they are actually needed, reducing the effective wake-up delay and improving memory access performance while still maintaining power savings for banks that remain unused.
3Loss of energy
If fine-grain power management is implemented, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The power gating control circuitry is designed to handle multiple functions using a unified architecture. The same control logic manages power gating for multiple banks, integrates bank address decoding, and coordinates with the memory control unit, reducing the need for separate dedicated circuits for each bank and overall simplifying the power management system while maintaining fine-grain control capability.
Data Source
AI summary
Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.