Power-Up Verification Circuit for Memory Systems
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Solution Overview
Problem
Memory systems, such as flash memory, face challenges in operating reliably under ultra-low voltage conditions during power-up, leading to potential failures and increased power-up latency in electronic devices.
Innovation Solution
A power-up verification circuit and state machine are introduced to detect the stability of circuit units during power-up, enabling the memory system to become operational even before the power voltage reaches a stable threshold by completing a sequence of detections and sending a verification completion signal to the memory control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system waits for the power voltage to reach the stable threshold before operating, then the operation reliability is improved, but the power-up latency increases
Solution Approach 1:
The power-up verification circuit performs detection and verification operations in advance during the power-up phase, before the power voltage reaches the stable threshold. The verification state machine executes a sequence of verification operations to check circuit unit stability proactively, allowing the memory system to transition to operational state earlier without compromising reliability.
Solution Approach 2:
The verification state machine continuously monitors the stability of circuit units during power-up and provides feedback signals. When all circuit units are verified as stable, a verification completion signal is generated to enable the memory control circuit to transition to operational state, creating a closed-loop control mechanism that balances early operation with reliability assurance.
2Loss of time
If the memory system operates under ultra-low voltage during power-up, then the power-up latency is reduced, but the operation reliability deteriorates due to unstable power or internal circuitry failure
Solution Approach 1:
The power-up verification circuit acts as an intermediary between the unstable power-up phase and the operational phase. It includes a verification state machine that coordinates verification operations across multiple circuit units, and a control mechanism that enables the memory control circuit only after successful verification, bridging the gap between early operation and reliable operation.
Solution Approach 2:
The system performs preliminary verification of circuit unit stability before enabling full operation. The verification state machine executes a predefined sequence of verification operations during the power-up phase to proactively identify and address potential instability issues before they affect operational reliability.
3Loss of time
If the memory control circuit is enabled early before power voltage stabilization, then the power-up latency is reduced, but the risk of circuit failure increases
Solution Approach 1:
The verification state machine implements continuous feedback monitoring of circuit unit stability during the power-up phase. It generates verification signals based on real-time stability assessments, enabling the memory control circuit only when all verification checks pass, thereby minimizing failure risk while achieving early operation.
Solution Approach 2:
The system performs preliminary stability verification of all circuit units before enabling the memory control circuit. This proactive verification process identifies potential failure conditions early, allowing the system to delay enablement only when necessary while achieving early operation in most cases.
Data Source
AI summary
A method facilitating a memory system operable in advance during power-up is introduced, including the following. A power-up verification circuit is provided, internally coupled to a memory control circuit of the memory system. During a period of the power-up in which a power voltage signal is ramping but not yet reaching a power voltage threshold, a power-up verification state machine of the power-up verification circuit is activated responsive to a power-on reset signal and the power voltage signal. The activated power-up verification state machine communicates with circuit units of the memory system to enable execution of corresponding detections on the circuit units in accordance with a sequence of states of the power-up verification state machine. After completion of the sequence of states, a verification completion signal is sent to enable the memory control circuit to be powered by the power voltage signal and operable to control the memory system.