Power Via Bar Height Profiling to Reduce Gate Capacitance
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Solution Overview
Problem
Standard power via bars in semiconductor devices create parasitic capacitance between gate ends, decreasing device performance.
Innovation Solution
The power via bar is designed with varying heights, recessed between gate ends and maintained at a higher height adjacent to source and drain regions, reducing parasitic capacitance while maintaining power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power via bar is made with uniform height across the device, then power delivery is maintained, but parasitic capacitance between gate ends increases
Solution Approach 1:
The power via bar is designed with non-uniform height where the height varies depending on the location. Specifically, the power via bar has reduced height in regions adjacent to gate ends to minimize parasitic capacitance, while maintaining full height in regions adjacent to source and drain regions to ensure adequate power delivery and electrical connection.
2Object-generated harmful factors
If the power via bar height is reduced adjacent to gate ends, then parasitic capacitance decreases, but power delivery capability may be compromised
Solution Approach 1:
The power via bar implements location-dependent height variations: reduced height adjacent to gate ends minimizes parasitic capacitance effects, while maintained full height adjacent to source and drain regions preserves power delivery capability and electrical connectivity to the backside power rail.
Solution Approach 2:
The power via bar is effectively segmented into different height zones along its length, with each zone optimized for its specific function: lower height zones near gates reduce capacitance, while higher height zones near sources/drains maintain power delivery.
Data Source
AI summary
One or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.