Power Via and Intermediate Layer Layout for BEOL Alignment

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Solution Overview

Problem

Semiconductor devices face mis-alignment issues with power via and source/drain patterns, leading to inefficiencies in power distribution and increased complexity in semiconductor architecture.

Innovation Solution

A semiconductor device design featuring an active device layer with source/drain patterns, insulating layers, and a back end of line (BEOL) structure, where power vias penetrate through intermediate and insulating layers to connect with the BEOL structure, with at least part of the power via's side surface in contact with an intermediate layer, improving electrical stability and alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power via penetrates through intermediate and insulating layers to connect BEOL structure with active device layer, then electrical stability is enhanced, but manufacturing precision requirements increase due to mis-alignment risks

Engineering Contradiction:
Improveelectrical stabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The intermediate layer serves as a mediator between the BEOL structure and the active device layer, providing a buffer zone that accommodates alignment tolerances. The power via contacts the intermediate layer on its side surface, allowing the intermediate layer to act as a positioning reference that reduces the impact of mis-alignment between the BEOL structure and source/drain patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the connection path into distinct segments: the BEOL structure, the intermediate layer, the insulating layers, and the active device layer. By segmenting the structure, each layer can be optimized independently for its specific function, and the intermediate layer specifically addresses the alignment issue by providing a separate reference plane.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240321689A1Semiconductor device
Publication Date: 2024.09.26 SAMSUNG ELECTRONICS CO LTD
  • US20240321689A1 patent drawing
  • US20240321689A1 patent drawing
  • US20240321689A1 patent drawing

AI summary

Provided is a semiconductor device including an active device layer including a plurality of source/drain patterns, a plurality of insulating layers on the active device layer, a back end of line (BEOL) structure on the plurality of insulating layers and configured to supply electric power to the active device layer, an intermediate layer between the plurality of insulating layers and the BEOL structure, and at least one power via penetrating through the intermediate layer and at least a part in each of the plurality of insulating layers in a vertical direction. The at least one power via electrically connects the BEOL structure and the active device layer. At least a part of a side surface of the at least one power via is in contact with the intermediate layer.