Power Via Layout for Noise-Isolated 3D Memory Interfaces
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Solution Overview
Problem
3D memory devices experience noise interference between power supply lines and signal input/output circuits due to simultaneous power consumption, affecting data transmission reliability and efficiency.
Innovation Solution
Incorporating groups of power vias and signal vias in a semiconductor device to provide stable power supply voltages while isolating signal vias from noise propagation, using through-substrate vias (TSVs) to connect interface and core chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large number of vertical vias are used to transfer signals at high transfer rates, then data transmission speed and bandwidth are improved, but simultaneous power consumption throughout the device increases causing noise on power supply lines
Solution Approach 1:
The device is segmented into distinct functional regions (memory array region and peripheral region) with separate power supply line configurations. Power supply lines in the memory array region are arranged differently from those in the peripheral region, allowing independent noise management for each region while maintaining high-speed data transmission capabilities.
Solution Approach 2:
Different power supply line configurations are applied to different regions based on their specific requirements. The memory array region receives power through vertically extending power supply lines, while the peripheral region uses power supply lines extending in a direction substantially perpendicular to the memory array region, optimizing both regions for high-speed operation while minimizing noise interference.
2Productivity
If memory core chips operate similar operations throughout circuits simultaneously at high transfer rates, then productivity is improved, but noise interference between memory array and peripheral regions increases
Solution Approach 1:
The power supply network is segmented into region-specific configurations that allow simultaneous high-speed operations in both memory array and peripheral regions without mutual noise interference. Each region has independently optimized power supply lines that prevent noise propagation between regions during concurrent operations.
Solution Approach 2:
The differently oriented power supply lines act as intermediaries that isolate the memory array region from the peripheral region electrically. This separation prevents noise generated in one region from interfering with operations in the other region, enabling simultaneous high-productivity operations throughout the device.
Data Source
AI summary
Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the peripheral region. The one or more wirings are disposed adjacent to the memory array region. One or more power vias of the plurality of power vias are disposed through a wiring of the one or more wirings.