PPAC Estimation Platform for IC Design Cycle Reduction
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Solution Overview
Problem
As IC technology advances and complexity increases, development cycles are delayed due to uncertainties in interface requirements and integration of analog blocks, leading to higher risks and longer manufacturing cycles.
Innovation Solution
An integrated platform that includes an IP bank, application bank, technology bank, model generator, and PPAC explorer to estimate performance, power, area, and cost (PPAC) for ICs, allowing for the selection of valid configurations and simulation of fabrication processes to expedite the development of mask sets and reduce development time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IC technology advances and chip complexity increases to achieve higher performance, then performance is improved, but development cycles are delayed and manufacturing risk increases
Solution Approach 1:
The patent performs PPAC estimation and fabrication process simulation in advance during the design phase, before actual manufacturing. This preliminary action identifies potential defects and optimizes configurations early, preventing delays during manufacturing and reducing development cycle time while maintaining high performance
2Manufacturing precision
If complete RTL-to-physical implementation is performed to ensure design accuracy, then manufacturing precision is improved, but development time and cost increase significantly
Solution Approach 1:
The patent creates virtual models and simulations of the IC design using PPAC estimation tools and fabrication process simulations. These virtual copies allow comprehensive validation and optimization without requiring complete physical implementation, significantly reducing development time while maintaining design accuracy through iterative virtual testing
3Reliability
If multiple configuration options are evaluated to optimize IC design, then design quality is improved, but the complexity of evaluation and development time increase
Solution Approach 1:
The patent implements automated PPAC estimation and fabrication process simulation systems that independently evaluate multiple configurations. The system self-performs the complex analysis of different design options, IP block configurations, and fabrication processes, reducing the burden on designers while comprehensively assessing design quality across multiple parameters
Data Source
AI summary
A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.