Wafer Level PPGA Copper Post LGA Package
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Solution Overview
Problem
Current wafer level chip scale packaging technologies rely on solder balls for BGA connections, which require complex tooling and processes, increasing costs and cycle time, and do not support fine pitch applications effectively.
Innovation Solution
The implementation of a land grid array (LGA) connection using copper posts and a molding compound to replace solder balls, reducing process complexity and enabling fine pitch applications while enhancing electrical performance and package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are used for BGA connection in wafer level chip scale packages, then electrical connection to PCB is achieved, but process complexity increases due to extra tooling and processes including ball placement, flux printing, clean, and reflow
Solution Approach 1:
The patent extracts and eliminates the solder ball component and its associated complex processes (ball placement, flux printing, clean, and reflow) from the packaging system. Instead, it uses a simplified copper post structure that directly provides electrical connection to the PCB without requiring the additional tooling and processing steps, thereby maintaining electrical reliability while reducing process complexity
Solution Approach 2:
The patent replaces the expensive and complex solder ball assembly process with a simpler, more cost-effective copper post structure. The copper posts are formed through a straightforward fabrication process that eliminates the need for specialized ball placement equipment and multiple processing steps, reducing both capital equipment investment and manufacturing complexity
2Reliability
If solder balls are used for BGA connection, then electrical connection is achieved, but manufacturing cost increases due to extra tooling and processes
Solution Approach 1:
The patent removes the costly solder ball component and its associated tooling requirements from the manufacturing system. The copper post structure provides the same electrical connection function through a simpler, more cost-effective fabrication process that eliminates the need for specialized ball placement equipment, flux printing equipment, and multiple processing steps, thereby reducing manufacturing cost while maintaining electrical reliability
Solution Approach 2:
The patent adopts a cost-effective copper post structure that replaces the expensive solder ball assembly process. The copper posts are formed through a straightforward fabrication process using standard semiconductor manufacturing equipment, eliminating the need for costly specialized tooling and reducing overall manufacturing expenses
3Reliability
If solder balls are used for BGA connection, then electrical connection is achieved, but cycle time increases due to multiple processing steps
Solution Approach 1:
The patent extracts and eliminates the time-consuming solder ball processes (ball placement, flux printing, clean, and reflow) from the manufacturing cycle. The copper post structure is formed through a streamlined fabrication process that integrates seamlessly with standard semiconductor manufacturing flows, significantly reducing the number of processing steps and overall cycle time while maintaining electrical connection reliability
4Device complexity
If copper post structure is used instead of solder balls, then process complexity is reduced, but manufacturing precision is required for fine pitch applications
Solution Approach 1:
The patent applies local quality by optimizing the copper post structure specifically for fine pitch applications. The copper posts are formed with precise dimensional control and appropriate spacing to accommodate fine pitch requirements. The structure incorporates local variations in post height, diameter, and spacing to meet the stringent precision demands of fine pitch applications while maintaining overall process simplicity
Data Source
AI summary
A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.


