Post-Passivation Interconnect Adhesion via Conductive Layer

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Solution Overview

Problem

Low-cost wafer level packaging (WLP) solutions without under bump metallization (UBM) layers face challenges in adhesion between solder balls and post-passivation interconnect (PPI) structures, leading to higher incidence of ball cracks.

Innovation Solution

A semiconductor device structure and method involving a contact pad, dummy pad, passivation layer, protective layer, and post-passivation interconnect (PPI) structure with a bump formed over the dummy pad, where the PPI structure includes a conductive layer and contact vias to enhance adhesion and prevent ball shift during reflow, using a molding compound to secure the bump and improve robustness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If UBM layers are used in WLP packages, then adhesion between solder balls and PPI structures is improved, but manufacturing cost increases

Engineering Contradiction:
Improveadhesion between solder balls and PPI structuresVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive UBM layers with a cost-effective alternative structure consisting of a conductive layer formed directly on the PPI structure. This conductive layer serves the same adhesion function but eliminates the need for multiple expensive metallization layers, achieving both cost reduction and maintained reliability

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent employs a composite structure combining the PPI structure with a specifically designed conductive layer that has optimized material properties for adhesion. This composite approach achieves reliable solder ball attachment without requiring traditional UBM layer stacks, resolving the cost-reliability tradeoff

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If UBM layers are removed to reduce cost, then manufacturing cost decreases, but adhesion between solder balls and PPI structures deteriorates

Engineering Contradiction:
Improvemanufacturing costVSAvoidadhesion between solder balls and PPI structures
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The conductive layer acts as an intermediary element between the PPI structure and the solder ball, providing the necessary adhesion interface. This intermediary layer compensates for the removal of UBM layers, maintaining reliability while reducing manufacturing cost

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the adhesion interface parameters by changing from traditional UBM layer composition to a simplified conductive layer structure. This parameter change optimizes the adhesion properties for solder ball attachment while eliminating costly materials and processes

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If low-cost WLP packages without UBM layers are used, then manufacturing cost decreases, but ball cracks increase

Engineering Contradiction:
Improvemanufacturing costVSAvoidball cracks
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The conductive layer serves as a cushioning layer that absorbs and distributes stress during solder ball reflow and cooling processes. This prior cushioning prevents ball cracks from forming, enabling low-cost packages without UBM layers to achieve reliable crack-free solder joints

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9443812B2Semiconductor device with post-passivation interconnect structure and method of forming the same
Publication Date: 2016.09.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9443812B2 patent drawing
  • US9443812B2 patent drawing
  • US9443812B2 patent drawing

AI summary

A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad.