Programmable Peripheral Interconnect Direct Event-Task Routing
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Solution Overview
Problem
Current microcontroller systems face inefficiencies in peripheral communication, including slow and unpredictable timings due to processor involvement, leading to significant energy consumption when waking the processor for inter-peripheral communication.
Innovation Solution
A programmable peripheral interconnect (PPI) system that allows direct communication between peripherals by mapping event signals to task registers, enabling task execution without processor intervention, and utilizing register addresses for channel configuration, allowing peripherals to communicate efficiently while the processor remains in a sleep state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor is used to relay messages between peripherals, then communication can be accomplished, but communication speed decreases and timing becomes unpredictable
Solution Approach 1:
The patent introduces a peripheral interconnect as an intermediary component that enables direct communication between peripherals without requiring processor intervention. The interconnect acts as a dedicated communication channel that bridges event-generating peripherals and task-receiving peripherals, eliminating the need for the processor to relay messages and thereby improving communication speed and predictability.
Solution Approach 2:
The patent segments the communication function by separating it from the processor. The peripheral interconnect is configured with dedicated event input channels and task output channels that are independent of the processor's interrupt and task management mechanisms. This segmentation allows peripherals to communicate directly through the interconnect while the processor maintains its own independent task execution.
2Productivity
If the processor is woken from sleep state to relay peripheral messages, then communication can occur, but energy consumption increases significantly
Solution Approach 1:
The peripheral interconnect serves as an intermediary communication path that allows peripherals to exchange signals without requiring the processor to be awake. The interconnect's event input channels receive signals from event-generating peripherals and route them through the interconnect logic to task-receiving peripherals, enabling communication while the processor remains in sleep state.
Solution Approach 2:
The peripheral interconnect enables peripherals to communicate with each other autonomously without requiring processor assistance. The interconnect's internal logic automatically routes event signals to the appropriate task registers based on configured mappings, allowing the system to maintain peripheral communication capability while the processor consumes minimal energy in sleep mode.
3Speed
If direct peripheral communication is enabled through an interconnect apparatus, then communication speed improves, but the system complexity increases
Solution Approach 1:
The peripheral interconnect is designed to handle multiple communication functions through a unified architecture. The same interconnect hardware handles different types of peripheral communications by configuring mappings between event inputs and task outputs. This multi-functionality reduces the need for separate dedicated communication paths for different peripheral pairs, thereby managing system complexity while maintaining high communication speed.
Solution Approach 2:
The peripheral interconnect employs dynamic configuration through software-programmable mappings that can be adjusted at runtime. The interconnect logic adapts its routing behavior based on configured mappings between event-generating peripherals and task-receiving peripherals. This dynamic configurability allows the system to optimize communication paths without requiring complex hardware redesign, managing system complexity while enabling fast direct peripheral communication.
Data Source
AI summary
Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).