Post-Passivation Interconnect Guard Rings for Wafer-Level Packaging

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional wafer-level packaging technologies face challenges in preventing mechanical stress and moisture penetration, particularly at the edges and corners of semiconductor dies, which can lead to mechanical failures of active and passive devices and interconnects.

Innovation Solution

The implementation of post-passivation interconnect (PPI) guard rings formed on top of passivation layers, using conductive materials like copper or copper alloys, which are electrically connected to bond pads and guard rings, helps to prevent stress and moisture penetration by forming a protective barrier around the circuit device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer-level packaging is used to reduce packaging time and cost, then productivity is improved, but mechanical stress and moisture penetration at edges and corners increase

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidmechanical stress and moisture penetration
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The conductive guard ring structure is formed beforehand during the wafer fabrication process, before the wafer is divided into individual dies and packaged. This pre-formed protective barrier cushions the edges and corners against mechanical stress and moisture penetration throughout the subsequent packaging and operation stages, enabling WLP's productivity benefits while mitigating its vulnerability to environmental factors.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9831196B2Methods and apparatus of guard rings for wafer-level-packaging
Publication Date: 2017.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9831196B2 patent drawing
  • US9831196B2 patent drawing
  • US9831196B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a passivation contact within the passivation layer, the passivation contact being over and electrically connected to the guard ring, forming a post-passivation interconnect (PPI) guard ring over the passivation layer and electrically connected to the passivation contact, and forming a first polymer layer over the PPI guard ring, the first polymer layer extending along a sidewall of the PPI guard ring.