Post-Passivation Interconnects with Polymer Plugs for CTE Mismatch

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Solution Overview

Problem

In the formation of wafer-level chip scale packages, there is a challenge with delamination between interconnect structures and polymer layers due to significant mismatch in Coefficient of Thermal Expansion (CTE), which occurs during thermal cycles, affecting the reliability of the post-passivation interconnects.

Innovation Solution

The formation of Post-Passivation Interconnect (PPI) plugs and polymer plugs within the polymer layers, which are aligned and spaced to reduce delamination by compensating for the thermal expansion mismatch, and are determined by local pattern density to optimize their formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If post-passivation interconnect structures are formed over metal pads with passivation layers, then electrical connectivity is achieved, but delamination occurs between interconnect structures and polymer layers due to CTE mismatch during thermal cycles

Engineering Contradiction:
Improvebonding reliabilityVSAvoidstructural integrity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The interconnect structure is divided into multiple segments including a base interconnect layer, multiple via layers (first via layer, second via layer), and intermediate polymer layers. This segmentation allows each layer to accommodate thermal expansion independently, reducing stress concentration and preventing delamination during thermal cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different materials with specific properties are used at different locations: the base interconnect layer uses conductive material for electrical connectivity, while intermediate polymer layers use materials with appropriate CTE values to match adjacent layers. The via structures are locally optimized with conductive fills in specific regions to manage thermal stress distribution.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple via layers and polymer layers are formed to reduce delamination, then bonding reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvebonding reliabilityVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple functions are combined into integrated structures: the via layers serve both as electrical interconnects and as stress management features. The polymer layers simultaneously provide mechanical support, electrical isolation, and CTE matching. This merging reduces the need for separate dedicated stress-relief structures.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The intermediate polymer layers serve multiple purposes: they provide mechanical support, electrical insulation, and most importantly, act as CTE transition layers between materials with different thermal expansion coefficients. The via structures similarly serve both electrical connectivity and thermal stress management functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The PPI and polymer plugs effectively reduce delamination between the interconnects and polymer layers, enhancing the reliability of the post-passivation interconnect structures by maintaining structural integrity through thermal cycles.

Implementation Method 1

delamination between interconnect structures and polymer layers due to significant mismatch in Coefficient of Thermal Expansion (CTE), which occurs during thermal cycles

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS9553066B2Post passivation interconnect structures and methods for forming the same
Publication Date: 2017.01.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9553066B2 patent drawing
  • US9553066B2 patent drawing
  • US9553066B2 patent drawing

AI summary

A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.