PPI Conductive Pattern Sidewall Shape for Controlled Pad Etching
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Solution Overview
Problem
The formation of post-passivation interconnect (PPI) structures in semiconductor devices is hindered by the accumulation of polymer residues during etching, leading to uneven etching rates and potential over-etching of conductive pads, which affects the structural integrity and performance of the PPI.
Innovation Solution
A method where the polymer layer formed during etching is not removed until the opening is complete, acting as a blocking layer to control the etching rate, resulting in a PPI structure with controlled dimensions and reduced stress at the bottom corners, enhancing thermal shock resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the polymer layer is continuously deposited during etching, then the etching rate is controlled and over-etching is prevented, but the manufacturing process complexity increases
Solution Approach 1:
The patent converts the harmful polymer residues that accumulate during etching into a beneficial blocking layer that controls the etching rate. By continuously depositing polymer material during the etching process, the polymer layer acts as a self-regulating barrier that prevents over-etching of the conductive pad, transforming what was previously a process defect into a process control mechanism.
Solution Approach 2:
The polymer layer serves as an intermediary between the etching process and the conductive pad. It mediates the etching rate by providing a controllable barrier that slows down the etching process near the conductive pad, allowing precise control of the opening formation without directly contacting or damaging the conductive pad structure.
2Productivity
If the polymer layer is removed continuously during etching, then the etching rate increases, but over-etching of the conductive pad occurs
Solution Approach 1:
Instead of removing the polymer layer to increase etching rate, the patent retains and continuously deposits the polymer layer to serve as a protective blocking layer. This approach prevents over-etching of the conductive pad while maintaining controlled productivity through the self-regulating nature of the polymer deposition process.
Solution Approach 2:
The continuous polymer deposition provides beforehand cushioning by building up a protective layer during the etching process itself. This cushioning effect prevents the etching process from penetrating too deeply into the conductive pad, ensuring structural integrity while maintaining efficient etching progress.
3Device complexity
If the opening is formed without a blocking layer, then the manufacturing process is simpler, but stress concentration occurs at the bottom corners of the PPI structure
Solution Approach 1:
The patent converts the polymer deposition step, which adds process complexity, into a solution that simultaneously addresses stress distribution issues. The polymer blocking layer modifies the stress distribution at the bottom corners of the PPI structure during formation, preventing stress concentration and improving structural stability.
Solution Approach 2:
By changing the physical and chemical parameters of the etching process through continuous polymer deposition, the patent alters the stress distribution characteristics of the formed structure. The polymer layer changes the mechanical properties and stress field during etching, resulting in improved stress distribution at critical locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures precise formation of the PPI structure with reduced over-etching, improving the structural integrity and thermal shock resistance of the semiconductor device.
Implementation Method 1
the polymer layer formed during etching is not removed until the opening is complete, acting as a blocking layer to control the etching rate
Data Source
AI summary
One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point.