Packet Processing Memory Controller Cache for SoC Latency Reduction
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Solution Overview
Problem
Existing content processing System on Chip (SoC) designs face significant performance bottlenecks due to the need for frequent data transfer between Packet Processing Controllers and external memory, leading to increased latency as the number of PPCs increases.
Innovation Solution
The integration of a Packet Processing Memory Controller Cache (PPMCC) with a 'Write Through' and 'Read Clear' policy, along with Quality of Service (QoS) tags and an Address Translation Lookup Table (ATLT), optimizes content processing by reducing latency and improving data throughput by caching packets within the SoC and dynamically allocating cache space based on packet priority and QoS information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If packets are transferred between Packet Processing Controllers and external memory, then data storage and retrieval is achieved, but latency increases and throughput decreases
Solution Approach 1:
The patent introduces a Packet Processing Cache (PPC) as an intermediary component between the Packet Processing Controllers and external memory. The PPC acts as a buffer that temporarily stores packet data, allowing controllers to read from and write to the cache without directly accessing external memory. This intermediary layer reduces the latency associated with external memory access while maintaining data throughput, as the cache provides faster access times compared to external memory.
Solution Approach 2:
The system performs preliminary actions by pre-fetching and caching packet data in the Packet Processing Cache before the Packet Processing Controllers need to access it. The cache proactively stores frequently accessed packet data, so when controllers need to process packets, the data is already available in the cache rather than requiring a time-consuming external memory access. This preliminary caching action reduces latency and improves throughput.
2Productivity
If the number of Packet Processing Controllers is increased to handle more traffic, then processing capacity is improved, but performance bottleneck worsens due to external memory access contention
Solution Approach 1:
The Packet Processing Cache serves as a shared intermediary resource that multiple Packet Processing Controllers can access simultaneously. Instead of all controllers competing for access to external memory, they can read from and write to the cache in parallel. This reduces the access latency that would otherwise increase with more controllers, as the cache provides a higher-speed access path that can handle multiple concurrent operations without the same bottlenecks as external memory.
3Reliability
If packets are stored in external memory for processing, then data persistence is achieved, but access frequency increases latency
Solution Approach 1:
The patent segments the storage system into two distinct layers: the Packet Processing Cache for frequent, fast access to active packet data, and external memory for persistent storage. This segmentation allows the system to maintain data persistence in external memory while simultaneously providing low-latency access to frequently accessed packets through the cache. The two-layer architecture resolves the contradiction by assigning different storage functions to different memory layers based on access patterns.
Data Source
AI summary
An apparatus and system provide an optimizing content processing throughput for systems on chips (“SoCs”). A Packet Processing Memory Controller Cache (“PPMCC”) on an SoC according to an embodiment of the present invention may enable the SoC to store content packets within the SoC, thus eliminating the need to write to and read from external memory. Additionally, by utilizing Quality of Service (“QoS”) tags for the content packets received by the SoC, PPMCC may enforce a unique caching policy which optimizing content processing. Finally, an Address Translation Lookup Table (“ATLT”) on the SoC enables packet processing controllers on the SoC to route packets directly amongst themselves by identifying the source and destination of each content packet.