Post-Package Repair Memory Row Remapping
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Solution Overview
Problem
Existing memory testing techniques require specific modifications to the memory controller and are not compatible with all hardware vendors, limiting their ability to validate error correction and post-package repair capabilities across a wide address range and distinguishing between correctable and uncorrectable errors.
Innovation Solution
The use of post-package repair (PPR) technology to remap memory transfer requests from a faulty row to a spare row with a predefined failure pattern, allowing for comprehensive testing of memory controllers' error handling capabilities without modifying the memory controller architecture, ensuring compatibility with any PPR-compatible memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing memory testing techniques are used, then memory controllers can be tested for error correction capabilities, but the techniques require specific modifications to the memory controller and are not compatible with all hardware vendors
Solution Approach 1:
The patent uses post-package repair (PPR) remapping as an intermediary mechanism to redirect memory access requests from a first row to a spare row with known failure patterns. This intermediary approach allows testing of error correction capabilities without requiring modifications to the memory controller architecture, thereby achieving both reliability validation and broad hardware compatibility.
2Measurement precision
If memory testing covers a wide address range, then comprehensive validation is achieved, but distinguishing between correctable and uncorrectable errors becomes more complex
Solution Approach 1:
The patent applies local quality by concentrating failure patterns in a specific spare row rather than distributing them across the entire address range. This allows the memory controller to be tested across a wide address range through PPR remapping while maintaining clear distinction between correctable and uncorrectable errors in the localized failure pattern region.
3Reliability
If comprehensive memory testing is performed, then error handling capabilities are validated, but modifications to existing memory modules and hardware vendors' specific designs are required
Solution Approach 1:
The patent leverages the memory module's own post-package repair capability to perform self-testing. By utilizing the built-in PPR functionality and spare rows that already exist in the memory module design, comprehensive error handling validation can be performed without requiring external modifications to the memory modules or hardware vendor designs.
Data Source
AI summary
In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.