Flexible PQC Accelerator Memory Reprovisioning for Constant Storage
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Solution Overview
Problem
Conventional hardware accelerators for post-quantum cryptography (PQC) algorithms are inflexible and inefficient in adapting to multiple algorithms due to large memory requirements, complex memory access patterns, and dynamic power consumption, lacking efficient coefficient storage and adaptability to changing control parameters.
Innovation Solution
A hardware accelerator architecture that provisions memory with constants values for a specific PQC algorithm and selectively updates these values based on control parameter matching, reducing memory size and power consumption by minimizing the need for software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hardware accelerators are designed for a single dedicated PQC algorithm, then they can provide dedicated optimization for that algorithm, but they lack flexibility to adapt to multiple PQC algorithms and future algorithm changes
Solution Approach 1:
The patent implements dynamic memory reconfiguration capability where the hardware accelerator can change its memory allocation and access patterns based on the specific PQC algorithm being executed. The system dynamically adapts its memory usage to match the requirements of different algorithms, allowing a single hardware design to efficiently support multiple algorithms without requiring separate dedicated memory configurations for each.
Solution Approach 2:
The patent changes memory access parameters such as bandwidth, latency, and addressing modes based on the detected PQC algorithm. By adjusting these parameters dynamically, the hardware accelerator optimizes its performance for each specific algorithm while using the same physical memory infrastructure, thereby achieving versatility without proportionally increasing hardware complexity.
2Productivity
If hardware accelerators use large memory to store constants values for PQC algorithms, then they can improve computation performance, but they increase power consumption and reduce flexibility
Solution Approach 1:
Instead of allocating memory for all possible PQC algorithm constants simultaneously (excessive action), the system loads only the necessary constants for the currently executing algorithm (partial action). This selective memory loading approach maintains high computation performance for the active algorithm while significantly reducing overall power consumption by keeping unused memory sections inactive or unpowered.
Solution Approach 2:
The system performs preliminary identification of the required PQC algorithm and pre-loads the necessary constants values into memory before the computation begins. This preliminary action ensures that when computation starts, the memory is already optimized for the specific algorithm, maintaining high performance without requiring large continuous memory allocations or sustained high power consumption.
3Reliability
If hardware accelerators are designed with fixed memory allocation for a specific algorithm, then they can optimize for that algorithm, but they cannot adapt to changing control parameters or future algorithm standardizations
Solution Approach 1:
The patent implements dynamic memory reconfiguration capability where the hardware accelerator can change its memory allocation and access patterns based on the specific PQC algorithm being executed. The system dynamically adapts its memory usage to match the requirements of different algorithms, allowing a single hardware design to efficiently support multiple algorithms without requiring separate dedicated memory configurations for each.
Solution Approach 2:
The system incorporates feedback mechanisms that detect changes in control parameters or algorithm requirements and automatically trigger memory reconfiguration. This feedback loop ensures that the memory allocation continuously adapts to the current operational needs, maintaining optimal performance for the active algorithm while preparing for future algorithm changes without requiring hardware redesign.
Data Source
AI summary
A hardware (HW) accelerator architecture is described that adapts to a number of post-quantum cryptography (PQC) algorithms. The architecture determines whether to re-provision memory that stores constants values for arithmetic computations used for executed PQC algorithms. The architecture enables only a single set of constants to be stored at any particular time and the memory only needs to have a capacity to ensure that the largest set of constants among one of several PQC algorithms is stored while obviating the need to store the constants used across all PQC algorithms.