Partial Response Decision Feedback Equalizer Distributed Control
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Solution Overview
Problem
High-speed electronic signaling between integrated circuit devices faces challenges due to timing delays in decision feedback equalization, particularly as signaling rates increase, making it difficult for circuitry to effectively utilize feedback representing the least latent prior data for ISI compensation.
Innovation Solution
A multi-phase partial response decision feedback equalizer with distributed control logic is implemented, using receiver circuitry and selection logic to generate conditional samples across multiple clock phases, minimizing timing delays by distributing output sample selection across multiple storage stages, allowing feedback signals to occur within a single time window of N/2 bit intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decision feedback equalization is used to compensate for inter-symbol interference, then ISI compensation is achieved, but timing delays increase as signaling rates increase, making it difficult for circuitry to effectively utilize feedback representing the least latent prior data
Solution Approach 1:
The equalizer is divided into multiple independent phases (first phase, second phase, third phase, fourth phase), each processing different sets of conditional samples. This segmentation allows parallel processing of feedback paths, reducing the critical timing path delay while maintaining effective ISI compensation through distributed decision feedback across phases.
Solution Approach 2:
The patent transitions from a single-phase sequential processing approach to a multi-phase parallel processing architecture. By adding the time dimension through multiple phases operating in parallel, the system reduces the effective feedback delay for each phase while maintaining comprehensive ISI compensation coverage.
2Productivity
If signaling rates are increased to improve data transmission speed, then productivity increases, but timing delays become too large for circuitry to react in time, making effective feedback utilization difficult
Solution Approach 1:
The high-speed data stream is segmented into multiple phases, each handling a portion of the conditional samples. This allows the circuitry to process feedback at manageable speeds within each phase while maintaining overall high data transmission rates through parallel operation of all phases.
Solution Approach 2:
The system dynamically assigns different conditional sample sets to different phases based on timing requirements. The multi-phase architecture allows flexible adaptation to different signaling rates by adjusting which phases are active and how conditional samples are distributed, optimizing the balance between transmission speed and circuitry reaction time.
3Measurement precision
If parallel decision paths are implemented for partial response methods, then data decision accuracy improves, but device complexity increases
Solution Approach 1:
The parallel decision paths are segmented into multiple phases, with each phase handling a specific set of conditional samples. This segmentation organizes the complexity into manageable units while maintaining the accuracy benefits of parallel processing through systematic distribution of decision-making across phases.
Solution Approach 2:
The patent resolves the complexity issue by transitioning from a single-plane parallel processing architecture to a multi-phase architecture. This adds a temporal dimension to the parallel processing, distributing the complexity across time phases while maintaining data decision accuracy through coordinated operation of all phases.
Data Source
AI summary
A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.