PRACH Signal Generation Using IFFT and Interpolation

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Solution Overview

Problem

5G NR and IoT devices face challenges in reducing power consumption during PRACH signal generation, especially for low data-rate and low latency scenarios, where frequent PRACH procedure execution increases power consumption.

Innovation Solution

The introduction of a PRACH control module that controls inverse Fourier transform, interpolation, and carrier frequency offset generators, allowing the replacement of computationally demanding IDFT with native IFFT modules and using interpolation to match the required sampling rate for DAC, reducing the size of IDFT and eliminating the need for dedicated engines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If IDFT is used to generate PRACH signal, then signal generation is achieved, but computational complexity and power consumption increase

Engineering Contradiction:
ImprovePRACH signal generation efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the mathematical parameter from IDFT to IFFT transformation, which allows using native power-of-two sized transforms that are more efficient in terms of computational complexity and power consumption while maintaining the same signal generation function

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent makes the IFFT module serve multiple functions: it generates PRACH signals and can also generate signals for other physical channels, eliminating the need for dedicated PRACH generation engines and reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If IDFT of large size is used to match DAC sampling rate, then sampling rate requirement is met, but computational complexity and storage requirements increase

Engineering Contradiction:
Improvesampling rate accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the signal generation process into two stages: first performing a small IFFT of power-of-two size to get preliminary samples, then using interpolation to generate the remaining samples to reach the required DAC sampling rate. This segmentation reduces computational complexity while maintaining sampling rate accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces interpolation as an intermediary step between the IFFT transformation and the final DAC input. The interpolation module acts as a mediator that expands the signal from a smaller sample set to the required sampling rate without requiring a large IFFT to begin with

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dedicated PRACH generation engines are used, then PRACH signal generation is reliable, but chip area and device complexity increase

Engineering Contradiction:
ImprovePRACH signal generation reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent designs a universal IFFT module that can generate PRACH signals as well as signals for other physical channels like PUSCH. This multi-functional approach maintains reliability through proper control mechanisms while significantly reducing the chip area by eliminating dedicated PRACH generation hardware

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11991029B2Physical random access channel signal generation optimization for 5G new radio
Publication Date: 2024.05.21 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11991029B2 patent drawing
  • US11991029B2 patent drawing
  • US11991029B2 patent drawing

AI summary

The present disclosure relates to a method for physical random access channel, PRACH, signal generation. The method comprises obtaining (S10) a first time-domain sequence (1010a) comprising a first set of time-domain samples. The method also comprises generating (S20) a second time-domain sequence (1040a) comprising a second set of time-domain samples, the second set of time-domain samples comprising the first set of time-domain samples and interpolated time-domain samples inserted between the samples of the first set of time-domain samples, the number of time-domain samples in the second set of time-domain samples matching a required number of samples needed for a digital-to-analogue converter, DAC, having a predetermined sampling rate, and providing (S50) the second time-domain sequence to the DAC. The present disclosure also relates to corresponding systems, user equipment, interpolation circuitry, PRACH control modules and associated methods, and computer program products.