PRAM Cell Array Write via Controller-Side Aggregation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase-change random access memory (PRAM) devices face high power consumption during write operations due to the effects of unselected memory cells, particularly in dense cross-point array architectures, which offsets their advantages over other memory technologies.
Innovation Solution
Implementing a memory system with a memory controller that performs block-level or sub-block-level write operations, including a reset phase to set memory cells to a high resistance state and a set phase to selectively set them to a low resistance state, thereby reducing power consumption by mitigating the impact of unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If word line-level write operations are used in dense cross-point array architectures, then device complexity is reduced and ease of operation is improved, but power consumption increases significantly due to unselected memory cells
Solution Approach 1:
The patent segments the memory array into blocks and further into sub-blocks, allowing write operations to be performed at the block level or sub-block level rather than at the word line level. This segmentation enables selective activation of smaller portions of the memory array, reducing the number of unselected cells that consume power during write operations. The controller is configured to manage these segmented structures and coordinate reset and set phases accordingly.
Solution Approach 2:
The patent implements a reset phase before the set phase in the write operation sequence. During the reset phase, memory cells in the selected block or sub-block are first reset to a known state (high resistance state) before the set phase writes data. This preliminary action ensures that all cells in the target area start from a consistent state, preventing unintended writes to unselected cells and reducing power consumption by limiting the impact of unselected cells to minimal levels.
2Loss of energy
If block-level or sub-block-level write operations are implemented, then power consumption is reduced by mitigating unselected cell effects, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The memory array is divided into blocks, which are further divided into sub-blocks, creating a hierarchical structure. The controller manages this segmentation by receiving write requests and determining the appropriate block or sub-block for data writing. This segmentation approach reduces power consumption by limiting the scope of operations to smaller regions, thereby reducing the number of unselected cells that consume power during write operations.
Solution Approach 2:
The controller performs a reset phase before the set phase, where it first resets the selected block or sub-block to a known state. This preliminary action simplifies the subsequent set phase by ensuring all target cells start from a consistent state, reducing the complexity of error handling and power management during the actual data writing operation.
3Reliability
If reset phase is performed before set phase in block-level operations, then write operation reliability is improved by ensuring consistent initial state, but loss of time increases due to additional operation steps
Solution Approach 1:
The reset phase is performed as a preliminary action before the set phase, ensuring that all memory cells in the selected block or sub-block are in a known initial state (high resistance state) before data writing begins. This preliminary reset action improves write operation reliability by preventing unintended writes to cells that should remain unchanged, and by ensuring consistent initial conditions for all cells in the target region.
Solution Approach 2:
The patent combines multiple write requests into a single block-level or sub-block-level operation. By aggregating multiple individual cell writes into a larger coordinated operation with a single reset phase, the system reduces the total number of separate reset operations that would otherwise be needed, thereby reducing overall time loss while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances energy efficiency by reducing power consumption during write operations, making PRAM devices more energy-efficient compared to traditional word line-level write operations.
Implementation Method 1
The phase-change material may be considered a programmable resistive material that can be readily transformed between a high-resistance state and a low-resistance state. Such a state transformation of the phase-change material occurs, for example, in response to a change in the temperature thereof, and the temperature change may be induced through resistive heating. Resistive heating may be accomplished, for example, by supplying current between ends of the phase-change material.
Data Source
AI summary
A memory system includes a memory controller; and a memory device including a memory cell array, which includes a plurality of bit lines and a plurality of blocks. Each block includes a plurality of word lines, and each word line includes a plurality of phase-change random access memory (PRAM) cells connected, respectively, to the plurality of bit lines. The memory controller is configured to buffer write requests each including write data and is configured to perform a write operation that includes a reset phase and a subsequent set phase. The reset phase includes erasing the PRAM cells included in first word lines from among the plurality of word lines included in a selected block, from among the plurality of blocks, and the set phase includes, after the reset phase, writing the write data from the buffered write requests to the PRAM cells of the first word lines.