PRAM Lower Electrode Formation via Mold Layer Templates
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Solution Overview
Problem
Conventional double patterning processes for manufacturing phase change random access memory (PRAM) devices require multiple photolithography steps, leading to increased manufacturing costs and time due to the complexity and high equipment costs associated with these processes.
Innovation Solution
A method involving the sequential formation of mold layer patterns and semiconductor patterns on a substrate, followed by trench formation and conformal deposition of lower electrode material, allowing for the separation of lower electrodes without the need for extensive photolithography, thereby minimizing the number of double patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double patterning processes are used to form fine patterns in PRAM devices, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to multiple photolithography steps
Solution Approach 1:
The patent segments the patterning process into distinct stages: forming mold layer patterns first, then using them as templates to create semiconductor patterns. This segmentation allows each stage to be optimized independently, reducing the need for multiple complex photolithography steps while maintaining fine pattern precision.
Solution Approach 2:
The patent introduces mold layer patterns as intermediary structures that mediate between the substrate and the final semiconductor patterns. These mold layers serve as temporary templates that guide the formation of lower electrodes and semiconductor regions, enabling precise pattern transfer without requiring extensive photolithography.
2Manufacturing precision
If multiple double patterning processes are performed to achieve fine patterns, then manufacturing precision is improved, but loss of time increases due to extended process duration
Solution Approach 1:
The patent performs preliminary actions by forming mold layer patterns and lower electrodes before creating the semiconductor patterns. This preliminary structuring establishes a template that guides subsequent pattern formation, eliminating the need for multiple iterative photolithography cycles and reducing overall manufacturing time.
Solution Approach 2:
The patent merges the formation of multiple structures (mold layers, lower electrodes, and semiconductor patterns) into a coordinated sequence where earlier structures serve dual purposes. The mold layers simultaneously act as structural elements and as patterning templates, combining multiple functions into fewer process steps.
3Manufacturing precision
If conventional double patterning processes are used, then manufacturing precision is improved, but ease of manufacture deteriorates due to high equipment costs and complex process sequences
Solution Approach 1:
The patent employs disposable mold layer patterns that are formed, used as templates, and then removed after serving their purpose. These temporary structures enable precise pattern formation without requiring expensive, complex photolithography equipment, as the mold layers can be created using simpler deposition and etching processes.
Solution Approach 2:
The patent replaces the optical-mechanical photolithography system with a more straightforward sequential deposition and etching process. Instead of using complex photomasks and light exposure systems, the invention uses direct physical deposition of mold layers and selective etching to achieve fine patterns, substituting optical mechanisms with simpler mechanical/chemical processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and time by minimizing the number of photolithography processes required, enabling the production of PRAM devices with fine patterns while maintaining efficiency and precision.
Implementation Method 1
depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench
Data Source
AI summary
A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.