PRAM Memory Device Segmented Arrays and Bit Sequence Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase change RAM (PRAM) devices face limitations in programming multiple memory cells due to the limited number of write drivers, which restricts the efficiency of data storage and retrieval processes.
Innovation Solution
A memory device with a program control circuit that simultaneously programs memory cells in unit cell arrays using a bit sequence scheme, optimizing the operation of write drivers to manage data programming across multiple columns, allowing for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple write drivers are used to program multiple memory cells simultaneously, then programming efficiency is improved, but the number of write drivers is limited by device constraints
Solution Approach 1:
The memory device is divided into multiple unit cell arrays, with each array independently programmable. This segmentation allows the system to program multiple memory cells simultaneously across different arrays using a limited number of write drivers, thereby improving overall programming efficiency without requiring a proportional increase in write driver count
Solution Approach 2:
The patent introduces a bit sequence scheme that operates across multiple time steps (temporal dimension) to program memory cells in different unit cell arrays sequentially. This allows the limited write drivers to service multiple arrays over time, effectively increasing programming capacity without adding more physical write drivers
2Productivity
If a bit sequence scheme is used to program memory cells across multiple unit cell arrays, then programming efficiency is improved, but the control complexity increases
Solution Approach 1:
The program control circuit pre-calculates and stores the bit sequence that determines which memory cells will be programmed in each time step. This preliminary preparation allows the complex multi-array programming operation to be executed systematically without real-time complex decision-making, reducing operational complexity
Solution Approach 2:
The system incorporates status signals from each unit cell array to track programming completion. The program control circuit uses this feedback information to determine when to transition between time steps and which arrays require programming, simplifying the control of the multi-array operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the programming efficiency of PRAM devices by optimizing the operation of write drivers, enabling simultaneous programming across multiple unit cell arrays, thereby improving data storage and retrieval processes.
Implementation Method 1
the phase change material causes a reversible phase change between a crystal state (i.e., low resistance) and an amorphous state (i.e., high resistance) by Joule heating occurred by a current or a voltage supplied to the phase change material
Implementation Method 2
the phase change material causes a reversible phase change between a crystal state (i.e., low resistance) and an amorphous state (i.e., high resistance)
Data Source
AI summary
In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.