PRAM Page Mode Control with Prefetch Register
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Solution Overview
Problem
Existing resistance-variable memory devices, such as phase-change random access memory (PRAM) devices, face challenges in optimizing data read operations to achieve faster and more efficient data retrieval, particularly in managing page modes and addressing/data pin configurations to minimize latency and maximize read speed.
Innovation Solution
The implementation of a resistance-variable memory device with a data register that prefetches read data and a page mode setting unit that allows for either sequential reading in a first page mode or reading after a start address is received in a second page mode, utilizing separate or shared address/data pins to optimize data output through a data output unit, enhancing read operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional read operations are used in resistance-variable memory devices, then the device structure remains simple, but the data retrieval speed is slow and latency is high
Solution Approach 1:
The patent implements a data register that prefetches read data from the memory cell array before it is actually needed for output. This preliminary action of fetching data in advance eliminates waiting time during read operations, significantly improving data retrieval speed without requiring fundamental changes to the memory cell structure itself
Solution Approach 2:
The patent divides the memory device into distinct functional units: memory cell arrays, data registers for prefetching, and output units for data transmission. This segmentation allows each component to operate independently and optimally, with the data register handling prefetching operations while the output unit manages data transmission, thereby improving overall read speed
2Productivity
If sequential reading mode is used for all page addresses, then the device operation is simple, but the time required to read multiple data sets is excessive
Solution Approach 1:
The patent implements a page mode setting unit that can dynamically switch between different reading modes (first page mode for sequential reading of all page addresses, and second page mode for reading only after a start address is received). This dynamic adaptability allows the device to optimize its operation based on the specific reading requirements, significantly improving productivity when reading multiple data sets
Solution Approach 2:
The patent creates a multi-functional read operation system that can handle both sequential reading of all page addresses and reading triggered by a start address. The same data register and output unit serve both reading modes, allowing the device to efficiently handle different data retrieval scenarios without requiring separate dedicated circuits for each mode
3Productivity
If separate address and data pins are used, then the pin configuration is simple and straightforward, but the device cannot optimize data output through shared pins
Solution Approach 1:
The patent implements a common address/data pin that serves dual functions: receiving page addresses during address phase and transmitting read data during data phase. This multi-functional pin configuration improves data output efficiency by reducing the total number of pins required while maintaining full functionality for both address input and data output operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the time required for reading multiple data sets by minimizing latency, allowing for faster and more efficient data retrieval in both synchronous and asynchronous read operations, thereby improving the overall performance of PRAM devices.
Implementation Method 1
a material phase of the phase-change material can be stably programmed to different resistive states by subjecting the material to heat treatment processes
Implementation Method 2
heat treatment processes (e.g., joule heating processes)
Data Source
AI summary
A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.