PRAM Programming Loop Control via Test Cell Verification

Solution Overview

Problem

Conventional Phase Change Random Access Memory (PRAM) devices require iterative programming loops to ensure data reliability, leading to increased programming time, reduced memory cell durability, and high power consumption.

Innovation Solution

A PRAM design that includes a test cell array, a write driver, a sense amplification and verification circuit, and a program loop control unit to omit unnecessary program loops, allowing for faster programming and reduced current consumption by storing program verification results and controlling the start of program loops based on these results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If iterative programming loops are used to ensure data reliability in PRAM, then programming reliability is improved, but programming time increases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary characterization of memory cells during manufacturing to determine their specific programming requirements. This preliminary action enables the system to skip unnecessary programming loops during normal operation, reducing programming time while maintaining reliability through pre-determined safe programming parameters for each cell.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through program verification operations that check whether programming was successful. The verification result feeds back to control the number of programming loops needed, allowing the system to stop early when programming is successful and avoid unnecessary iterations, thus reducing overall programming time while ensuring reliability.

Inventive Principle:

Principle #23Feedback

2Reliability

If iterative programming loops are used to ensure data reliability in PRAM, then programming reliability is improved, but power consumption increases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary characterization of memory cells during manufacturing to determine their specific programming requirements. This preliminary action enables the system to skip unnecessary programming loops during normal operation, reducing power consumption while maintaining reliability through pre-determined safe programming parameters for each cell.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through program verification operations that check whether programming was successful. The verification result feeds back to control the number of programming loops needed, allowing the system to stop early when programming is successful and avoid unnecessary iterations, thus reducing overall power consumption while ensuring reliability.

Inventive Principle:

Principle #23Feedback

3Reliability

If iterative programming loops are used to ensure data reliability in PRAM, then programming reliability is improved, but memory cell durability decreases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidmemory cell durability

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent performs preliminary characterization of memory cells during manufacturing to determine their specific programming requirements. This preliminary action enables the system to skip unnecessary programming loops during normal operation, reducing the total number of write cycles and extending memory cell durability while maintaining reliability through pre-determined safe programming parameters for each cell.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through program verification operations that check whether programming was successful. The verification result feeds back to control the number of programming loops needed, allowing the system to stop early when programming is successful and avoid unnecessary iterations, thus reducing overall wear on memory cells and extending durability while ensuring reliability.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces overall programming time and current consumption by eliminating unnecessary loops, thereby enhancing programming speed and memory cell durability while minimizing power usage.

Implementation Method 1

PRAM is a nonvolatile memory device that uses a changeable phase state (e.g., a resistance property) which is response to an applied temperature condition

Methodology Applied

Scientific EffectPhase change: Phase Change

Implementation Method 2

the state of the phase change material is defined by the application of a heating current through the bit line BL

Methodology Applied

Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS7573758B2Phase-change random access memory (PRAM) performing program loop operation and method of programming the same

Publication Date: 2009.08.11 SAMSUNG ELECTRONICS CO LTD

AI summary

A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data, and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation.