PRAM Redundancy Testing via Bank Segmentation
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Solution Overview
Problem
Highly integrated phase-change random access memory (PRAM) devices face operational errors due to cell defects, leading to longer access times for redundancy cells during testing, as the number of input/output lines for transmitting test data is limited, and redundancy cell tests require more time than conventional cell tests.
Innovation Solution
The PRAM device incorporates a plurality of banks, column redundancy cell arrays, and column redundancy write drivers, allowing simultaneous transmission of redundancy test data to corresponding cell arrays in response to a test control signal, with each bank activating multiple input/output lines for program pulses to increase testing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy cell test operations are performed using conventional methods, then cell defects can be detected, but access time increases significantly due to limited input/output lines
Solution Approach 1:
The memory device is divided into multiple banks, with each bank containing its own dedicated redundancy cell array and write driver. This segmentation allows parallel testing operations across different banks simultaneously, reducing overall access time while maintaining comprehensive defect detection capability through dedicated test data transmission paths in each bank.
2Device complexity
If a single redundancy cell array is used for all banks, then device complexity is reduced, but testing speed decreases due to shared input/output lines
Solution Approach 1:
Each bank is assigned its own dedicated redundancy cell array and write driver, creating separate testing pathways for each bank. This segmentation enables simultaneous testing operations across multiple banks without sharing input/output lines, thereby increasing testing speed while keeping the structural complexity manageable through modular bank-level redundancy units.
3Productivity
If redundancy cell arrays are added to each bank, then testing speed increases through parallel operations, but device complexity increases
Solution Approach 1:
The redundancy cell arrays and write drivers in each bank serve multiple functions: they enable parallel testing operations to increase speed, provide defect detection for cell defects, and maintain data integrity through redundancy. This multi-functionality justifies the added complexity by delivering multiple benefits from the same structural additions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster redundancy cell testing and access by writing redundancy test data simultaneously with normal data, reducing the time required for redundancy cell tests and maintaining access speed despite shared resources.
Implementation Method 1
a phase-change material (Ge—Sb—Tb) of a PRAM cell may transition between a crystalline state and an amorphous state depending on the temperature and/or duration of heating applied to the phase-change material, thereby storing data in the PRAM cell
Implementation Method 2
Such high temperatures may be obtained by Joule heating caused by current flowing through the PRAM cell
Data Source
AI summary
A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.