Phase-change memory repair mode switching
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Solution Overview
Problem
Phase-change random access memories (PRAMs) face inefficiencies and reliability issues in repairing failed memory columns, particularly when failures occur to multiple columns using different input/output paths, as existing repair modes either repair columns one by one (×1 mode) or two by two (×2 mode), leading to varying reliability and efficiency based on failure locations.
Innovation Solution
A phase-change random access memory system that includes a memory block with multiple memory columns using different input/output paths, a redundancy memory block with corresponding redundancy columns, and an input/output controller that adapts the number of columns repaired based on an input/output repair mode control signal, utilizing column address fuse boxes, control fuse boxes, and path selection circuits to selectively enable redundancy paths for efficient repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If failed memory columns are repaired one by one in ×1 mode, then repair efficiency is improved, but reliability deteriorates when multiple columns fail
Solution Approach 1:
The patent implements dynamic switching between ×1 and ×2 repair modes based on the actual failure situation. The system can adaptively change the repair strategy from repairing one column at a time to repairing two columns simultaneously, optimizing both efficiency and reliability according to the number and location of failures.
Solution Approach 2:
The patent changes the repair mode parameter (from ×1 to ×2) depending on the failure configuration. When two memory columns at the same column address but different I/O paths fail, the system switches to ×2 mode to repair both columns simultaneously using respective redundancy columns, thereby improving reliability while maintaining efficient repair operations.
2Reliability
If failed memory columns are repaired two by two in ×2 mode, then reliability is improved, but repair efficiency decreases
Solution Approach 1:
The system dynamically selects between ×1 and ×2 repair modes based on the failure pattern. The ×2 mode is activated only when two specific columns (same column address, different I/O paths) fail, while other scenarios use ×1 mode, thus achieving high reliability only when needed while maintaining overall repair efficiency.
Solution Approach 2:
The repair mode parameter is changed from ×1 to ×2 specifically when the failure condition matches the ×2 mode requirements (two columns at same address with different I/O paths). This conditional parameter change ensures reliability improvement is achieved at the minimum necessary cost to repair efficiency.
3Adaptability or versatility
If redundancy memory columns are used to replace failed columns, then repair capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory structure into regular memory columns and separate redundancy memory columns. This segmentation allows the redundancy columns to be independently activated only when failures occur, providing repair capability without permanently increasing the operational complexity of the memory system.
Solution Approach 2:
The redundancy memory columns act as intermediary elements that can replace failed regular columns. These intermediary columns are managed through control logic that determines when and how to activate them, providing repair capability while isolating the complexity of the repair mechanism from the normal memory operation.
Data Source
AI summary
A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.